Abstract: The present disclosure relates to a charging guidance method for fast charging loads based on an adjustable and graded charging service fee, including: establishing a fast charging load prediction model based on a trip chain and a Monte Carlo method to predict a fast charging demand and a spatial-temporal trajectory change of a user trip; deciding a charging location based on a weighted user charging location decision model, and calculating a fast charging load of each charging station; constructing a regional graded charging service fee adjustment model with a minimum sum of absolute values of voltage deviations of nodes in the distribution network in a region as an optimization objective, and optimizing and adjusting the charging service fee; and determining an optimal user charging location under fast charging loads by using the weighted user charging location decision model based on the adjusted charging service fee.

Abstract: Disclosed is an optical device (10) comprising a plurality of lenses (100) for projecting a plurality of parallel beams (202, 204) having a predetermined width towards an object area, wherein each lens comprises a lens body including a cavity (150) for housing a solid state lighting element (200); a pair of opposing internally reflecting side surfaces (130) for constraining said beam within said predetermined width; and a light exit surface delimited by said opposing side surfaces, the light exit surface comprising a curved region (110) extending from a first further side surface (141) extending between the opposing side surfaces and shaped to generate a collimated beam portion along an optical axis; and a stepped region in between the curved region and a second further side surface (142) extending between the reflecting side surfaces, wherein said steps are defined by a plurality of prismatic protrusions (120), each of said protrusions laterally extending between said opposing side surfaces.

Abstract: The invention provides a lighting system for providing illumination on a surface (16), comprising a first array (10) of light sources (13) and a first reflector (12) for forming a first pattern on the surface, and a second array (10) of light sources (13) and a second reflector (12) for forming a second pattern on the surface (16), arranged concentrically around the first pattern. A controller (44) controls the first and second arrays (10) of light sources (13) to apply a cyclic function thereby to define one or more radially propagating rings or partial rings of illumination on the surface (16). This is enables a dynamic ripple lighting effect to be provided on the surface (16).

Abstract: The invention provides a lighting system for providing illumination on a surface (16), comprising a first array (10) of light sources (13) and a first reflector (12) for forming a first pattern on the surface, and a second array (10) of light sources (13) and a second reflector (12) for forming a second pattern on the surface (16), arranged concentrically around the first pattern. A controller (44) controls the first and second arrays (10) of light sources (13) to apply a cyclic function thereby to define one or more radially propagating rings or partial rings of illumination on the surface (16). This is enables a dynamic ripple lighting effect to be provided on the surface (16).

Abstract: Disclosed is an optical device (10) comprising a plurality of lenses (100) for projecting a plurality of parallel beams (202, 204) having a predetermined width towards an object area, wherein each lens comprises a lens body including a cavity (150) for housing a solid state lighting element (200); a pair of opposing internally reflecting side surfaces (130) for constraining said beam within said predetermined width; and a light exit surface delimited by said opposing side surfaces, the light exit surface comprising a curved region (110) extending from a first further side surface (141) extending between the opposing side surfaces and shaped to generate a collimated beam portion along an optical axis; and a stepped region in between the curved region and a second further side surface (142) extending between the reflecting side surfaces, wherein said steps are defined by a plurality of prismatic protrusions (120), each of said protrusions laterally extending between said opposing side surfaces.

Abstract: A circuit for generating USB peripheral clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a receiving counter and a frequency division controller, wherein the internal oscillator generates a clock having a fixed frequency; the controllable frequency divider processes frequency division on the clock generated by the internal oscillator; the frequency multiplier processes frequency multiplication on the clock after frequency division and transmits the clock after frequency multiplication to the USB main structure; the receiving counter receives an SOF packet which is transmitted by a host according to the clock outputted by the frequency multiplier, and counts intervals of receiving the SOF packet; and the frequency division controller compares the difference between the counting result of the receiving counter and a standard interval, controls and regulates frequency division parameters of the controllable frequency divider according to a comparing result thereo

Abstract: A circuit for producing USB host working clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a USB host interface, and a frequency division controller. According to the frequency multiplier providing clock, the USB host interface configures with USB peripherals for responding. The frequency division controller is connected to the USB host interface and the controllable frequency divider. The USB host interface transmits a response result that the USB host interface configures with USB peripherals for responding to the frequency division controller. According to the USB host interface feeding back the response result, the frequency division controller regulates a frequency dividing ratio of the controllable frequency divider in set scope of the frequency dividing ratio.

Abstract: A circuit for generating a peripheral clock for USB, provided on a USB major structure, comprises an internal oscillator, a receiver, a transmitter, a clock counter, and a clock processor; wherein the internal oscillator generates a clock having a settled frequency; the receiver is connected with the internal oscillator and a system unit, and receives a packet transmitted by the system unit; the transmitter is connected with the internal oscillator and the system unit, and transmits a packet of the USB major structure to the system unit; the clock counter is connected with the receiver and the internal oscillator, and counts a length of the packet received; and the clock processor is connected with the clock counter, the internal oscillator, and the transmitter, and controls and adjusts a length of the packet transmitted by the transmitter according to the length of the packet counted by the clock counter.

Abstract: A shift frequency demultiplier includes: an inverter; N-2 registers; and N-4 OR gates; wherein an output terminal of the No. N-2 register is connected to an input terminal of the inverter, an output terminal of the inverter is connected to an input terminal of the No. 1 register and input terminals of the OR gates; the output terminal of the No. 1 register is connected to another input terminal of the No. 1 OR gate, the output terminal of the No. N-4 register is connected to another input terminal of the No. N-4 OR gate; an output terminal of the No. 1 OR gate is connected to the input terminal of the No. 2 register, an output terminal of the No. N-4 OR gate is connected to the input terminal of the No. N-3 register whose the output terminal is connected to an input terminal of the No. N-2 register.

Abstract: A circuit for producing USB host working clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a USB host interface, and a frequency division controller. According to the frequency multiplier providing clock, the USB host interface configures with USB peripherals for responding. The frequency division controller is connected to the USB host interface and the controllable frequency divider. The USB host interface transmits a response result that the USB host interface configures with USB peripherals for responding to the frequency division controller. According to the USB host interface feeding back the response result, the frequency division controller regulates a frequency dividing ratio of the controllable frequency divider in set scope of the frequency dividing ratio.

Abstract: A divider logic circuit for obtaining a quotient S of a dividend M divided by a divisor N, includes a first constant value input terminal, a first adder, a second constant value input terminal, a base number input terminal, at least one integer power device, at least one right shift register, a second adder, and a multiplier; wherein the integer power device determines a first constant value that the base number is N1?N, and the exponent is i?1; wherein the right shift registers shift the first constant value to the right for h*i-digit for outputting a second constant value; wherein the multiplier multiplies a third constant value by the constant value M?N*S1 for outputting a fourth constant value, wherein the first adder adds up the estimate S1 and the fourth constant value for outputting the quotient S. The present invention also provides an implement method therefor.

Abstract: A circuit for generating USB peripheral clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a receiving counter and a frequency division controller, wherein the internal oscillator generates a clock having a fixed frequency; the controllable frequency divider processes frequency division on the clock generated by the internal oscillator; the frequency multiplier processes frequency multiplication on the clock after frequency division and transmits the clock after frequency multiplication to the USB main structure; the receiving counter receives an SOF packet which is transmitted by a host according to the clock outputted by the frequency multiplier, and counts intervals of receiving the SOF packet; and the frequency division controller compares the difference between the counting result of the receiving counter and a standard interval, controls and regulates frequency division parameters of the controllable frequency divider according to a comparing result thereo

Abstract: A circuit for generating a peripheral clock for USB, provided on a USB major structure, comprises an internal oscillator, a receiver, a transmitter, a clock counter, and a clock processor; wherein the internal oscillator generates a clock having a settled frequency; the receiver is connected with the internal oscillator and a system unit, and receives a packet transmitted by the system unit; the transmitter is connected with the internal oscillator and the system unit, and transmits a packet of the USB major structure to the system unit; the clock counter is connected with the receiver and the internal oscillator, and counts a length of the packet received; and the clock processor is connected with the clock counter, the internal oscillator, and the transmitter, and controls and adjusts a length of the packet transmitted by the transmitter according to the length of the packet counted by the clock counter.

Abstract: A divider logic circuit for obtaining a quotient S of a dividend M divided by a divisor N, includes a first constant value input terminal, a first adder, a second constant value input terminal, a base number input terminal, at least one integer power device, at least one right shift register, a second adder, and a multiplier; wherein the integer power device determines a first constant value that the base number is N1?N, and the exponent is i?1; wherein the right shift registers shift the first constant value to the right for h*i-digit for outputting a second constant value; wherein the multiplier multiplies a third constant value by the constant value M?N*S1 for outputting a fourth constant value, wherein the first adder adds up the estimate S1 and the fourth constant value for outputting the quotient S. The present invention also provides an implement method therefor.

Abstract: A portable electronic device includes a first cover, a second cover and a connecting mechanism connecting the first cover with the second cover. The connecting mechanism includes a fixing base fixed on the first cover, a turning base fixed on the second cover, a first linking board rotatably connected to the fixing base and the turning base, a second linking board rotatably connected to the fixing base and the turning base. The fixing base, the first linking board, the turning base and the second linking board collectively form a four-bar linkage mechanism. The connecting mechanism further includes an arc spring urged between the second linking board and the fixing base to supply an elastic force to the four-bar linkage mechanism.

Abstract: A shift frequency demultiplier with automatic reset function is N-frequency demultiplication (N>2) and includes N-1 registers connected with each other and defined from a first register to an (N-1)th register. Each of the registers has an input end, an output end, a reset end and a clock end. For the registers from the first register to the (N-2)th register, the output end of every register is connected with the input end of a next register adjacent thereto, the output end of the (N-1)th register is connected with the input end of the first register by a reverser. The reset end of the (N-1)th register is connected with a system reset signal end. The system reset signal end logically multiplied by the output end of the (N-1)th register is connected with the reset ends of the registers from the first register to the (N-2)th register.

Abstract: A portable electronic device includes a first cover, a second cover and a connecting mechanism connecting the first cover with the second cover. The connecting mechanism includes a fixing base fixed on the first cover, a turning base fixed on the second cover, a first linking board rotatably connected to the fixing base and the turning base, a second linking board rotatably connected to the fixing base and the turning base. The fixing base, the first linking board, the turning base and the second linking board collectively form a four-bar linkage mechanism. The connecting mechanism further includes an arc spring urged between the second linking board and the fixing base to supply an elastic force to the four-bar linkage mechanism.

Abstract: The present invention discloses a memory build-in self-test comprising steps of: (a) determining whether there is redundant address in the ROM; (b) when there is redundant address for storing standard check code, transferring the coefficient file in the ROM to a predetermined format; (c) producing a self-test logic and a standard check code corresponding to the ROM via design tool; (d) writing the standard check code into the redundant address and generating a new ROM. The present invention can assure that the standard check code and coefficient can be simply revised via corresponding way of Mask Change, so as to detect the damages of ROM by using memory build-in self-test (MBIST) which does not need to remake a whole set of Mask to revise the standard check code outside the ROM, so as to save cost and time, and lower the difficulty to update the product.

Abstract: A shift frequency demultiplier with automatic reset function is N-frequency demultiplication (N>2) and includes N-1 registers connected with each other and defined from a first register to an (N-1)th register. Each of the registers has an input end, an output end, a reset end and a clock end. For the registers from the first register to the (N-2)th register, the output end of every register is connected with the input end of a next register adjacent thereto, the output end of the (N-1)th register is connected with the input end of the first register by a reverser. The reset end of the (N-1)th register is connected with a system reset signal end. The system reset signal end logically multiplied by the output end of the (N-1)th register is connected with the reset ends of the registers from the first register to the (N-2)th register.

Abstract: A signal conditioning system includes a first filter, a signal processing module connected with the first filter, a second filter connected with the signal processing module, and a ?-? modulator connected with the second filter. The signal processing module makes the saturation overflow treatment to the signal output by the first filter using the characteristics of the radix complement adder. The ?-? modulator is a high order filter formed by a plurality of cascaded and inter-stage feedback second-order filters. Based on the performance of the ?-? modulator and the whole system, the stability of the signal conditioning system is improved.