Patents by Inventor Xiushan Feng
Xiushan Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9069762Abstract: An approach is provided in which an equivalence class generator selects a configurable module that includes control points and configuration parameters. The configuration parameters define a parameter state space of the configurable module. The equivalence class generator utilizes the control points to generate equivalence classes, which include class representatives that indicate values for the configuration parameters. Next, one of the class representatives are selected and verified from each of the equivalence classes. In turn, the verification of the class representatives verifies the parameter state space of the configurable module.Type: GrantFiled: June 22, 2012Date of Patent: June 30, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Xiushan Feng, Yinfang Lin, Jayanta Bhadra
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Patent number: 9043737Abstract: A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.Type: GrantFiled: April 30, 2013Date of Patent: May 26, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Jayanta Bahadra, Xiushan Feng, Xiao Sun
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Patent number: 9002694Abstract: An approach is provided in which a power design verification system retrieves a power intent data corresponding to a power design, which identifies the power design's power modes and power mode transition conditions. The power design verification system selects one of the power mode transition conditions, which identifies input signals that invoke a transition from a first power mode to a second power mode. In turn, the power design verification system generates simulation stimuli based upon the identified input signals and simulates the power design utilizing the generated simulation stimuli accordingly.Type: GrantFiled: May 3, 2012Date of Patent: April 7, 2015Assignee: Freescale Semiconductors, Inc.Inventors: Xiushan Feng, Jayanta Bhadra, Scott R. Little
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Publication number: 20140325463Abstract: A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.Type: ApplicationFiled: April 30, 2013Publication date: October 30, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Jayanta Bahadra, Xiushan Feng, Xiao Sun
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Publication number: 20130346375Abstract: An approach is provided in which an equivalence class generator selects a configurable module that includes control points and configuration parameters. The configuration parameters define a parameter state space of the configurable module. The equivalence class generator utilizes the control points to generate equivalence classes, which include class representatives that indicate values for the configuration parameters. Next, one of the class representatives are selected and verified from each of the equivalence classes. In turn, the verification of the class representatives verifies the parameter state space of the configurable module.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Inventors: Xiushan Feng, Yinfang Lin, Jayanta Bhadra
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Patent number: 8584063Abstract: An approach is provided in which a computing system retrieves a design description that corresponds to an electronic circuit design. The computing system selects an assertion corresponding to the electronic circuit design, which includes one or more assertion signal identifiers corresponding to one or more description signal points included in the design description. Next, the computing system creates a partitioned region from the design description based upon the description signal points. The computing system compiles and verifies the partitioned region that, in turn, verifies the electronic circuit design.Type: GrantFiled: September 7, 2012Date of Patent: November 12, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Xiushan Feng, Jayanta Bhadra, Ross L. Patterson
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Publication number: 20130297280Abstract: An approach is provided in which a power design verification system retrieves a power intent data corresponding to a power design, which identifies the power design's power modes and power mode transition conditions. The power design verification system selects one of the power mode transition conditions, which identifies input signals that invoke a transition from a first power mode to a second power mode. In turn, the power design verification system generates simulation stimuli based upon the identified input signals and simulates the power design utilizing the generated simulation stimuli accordingly.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Inventors: Xiushan Feng, Jayanta Bhadra, Scott R. Little
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Patent number: 8555226Abstract: An approach is provided in which a formal verification tool sends a condition signal to a first circuit instance and to a second circuit instance, which are both instances of an electric circuit design. The formal verification tool selects a common input port and sends a first input value to the common input port of the first circuit instance and sends a second input value, which is different than the first input value, to the common input port of the second circuit instance. In turn, the first circuit instance generates a first output value and the second circuit instance generates a second instance value, which are utilized to verify dependencies between the electronic circuit's input ports and output ports.Type: GrantFiled: September 4, 2012Date of Patent: October 8, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Xiushan Feng, Jayanta Bhadra, Ashish Goel
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Patent number: 7954075Abstract: One set of illegal vector sequences is manually generated for a circuit design and a symbolic simulator is used to automatically generate another set of illegal vector sequences for the circuit design. For verification purposes, the relationship between the manually generated set and the automatically generated set is determined. Prior to determining this relationship, one or both of the sets are simplified. One simplification technique includes replacing pairs of illegal vector sequences that are the same except at one bit position with a more general illegal vector sequence representative of both illegal vector sequences of the pair.Type: GrantFiled: June 6, 2008Date of Patent: May 31, 2011Assignee: Advanced Micro Devices, Inc.Inventor: Xiushan Feng
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Publication number: 20090307643Abstract: One set of illegal vector sequences is manually generated for a circuit design and a symbolic simulator is used to automatically generate another set of illegal vector sequences for the circuit design. For verification purposes, the relationship between the manually generated set and the automatically generated set is determined. Prior to determining this relationship, one or both of the sets are simplified. One simplification technique includes replacing pairs of illegal vector sequences that are the same except at one bit position with a more general illegal vector sequence representative of both illegal vector sequences of the pair.Type: ApplicationFiled: June 6, 2008Publication date: December 10, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventor: Xiushan Feng