Patents by Inventor Xiuting C. Man
Xiuting C. Man has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230205304Abstract: A system and method for efficient power management of an integrated circuit are described. In various implementations, a computing system includes an integrated circuit, multiple voltage regulators, and circuitry that detects when current drawn from a power rail from one of the multiple voltage regulators exceeds a limit. Upon detection, a single global alarm signal is asserted and conveyed to the integrate circuit. The integrated circuit includes at least a first group of functional blocks sharing a first power rail and a second group of functional blocks sharing a second power rail. When the global alarm signal is asserted, the functional blocks of the first group and the second group perform steps to immediately reduce power consumption. In order to maintain performance and satisfy a quality of service (QoS) parameter, a power management controller of the integrated circuit reassigns power limits shortly thereafter.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Inventors: Xiuting C. Man, Xiaojie He, Michael Leonard Golden, Richard M. Born
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Patent number: 11016916Abstract: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.Type: GrantFiled: May 7, 2020Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Xiuting C. Man, Jeremy J. Shrall, Deepak Ganapathy, Dorit Shapira
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Patent number: 10754404Abstract: In an embodiment, a processor includes a first power rail, a first component coupled to the first power rail, and a compensation control unit. The compensation control unit is to: detect a request to change a voltage level of the first power rail by a first voltage change amount; in response to detecting the request, determine that the first voltage change amount exceeds a first threshold level associated with the first component; and in response to determining that the first voltage change amount exceeds the first threshold level, initiate a first compensation action prior to changing the voltage level of the first power rail. Other embodiments are described and claimed.Type: GrantFiled: September 30, 2016Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Xiuting C. Man, Amir Ali Radjai, Jeremy J. Shrall
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Patent number: 10657083Abstract: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.Type: GrantFiled: September 30, 2016Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Xiuting C. Man, Jeremy J. Shrall, Deepak Ganapathy, Dorit Shapira
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Patent number: 10345884Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: GrantFiled: August 16, 2016Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don C. Soltis, Jr., Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Patent number: 10083735Abstract: Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value.Type: GrantFiled: April 25, 2017Date of Patent: September 25, 2018Assignee: INTEL CORPORATIONInventors: Xiuting C. Man, Stanley S. Kulick
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Patent number: 9851771Abstract: Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.Type: GrantFiled: December 28, 2013Date of Patent: December 26, 2017Assignee: Intel CorporationInventors: Lawrence A Cooper, Justin J Song, Xiuting C Man, Nagi Aboulenein, Christopher E Cox, Rebecca Z Loop
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Patent number: 9653144Abstract: Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value.Type: GrantFiled: June 28, 2016Date of Patent: May 16, 2017Assignee: Intel CorporationInventors: Xiuting C. Man, Stanley S. Kulick
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Patent number: 9507408Abstract: Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (Vtt) with power gating circuitry to selectively gate the termination supply voltage in response to a power gating control signal (VttControl) is coupled with a processing core coupled with the memory device, the processing core to selectively assert and deassert the VttControl signal.Type: GrantFiled: September 27, 2012Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: Xiuting C. Man, Christopher P. Mozak, Shaun M. Conrad, Jeffery L. Krieger, Philip R. Lehwalder, Inder M. Sodhi
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Patent number: 9417681Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: GrantFiled: April 27, 2015Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Patent number: 9189046Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.Type: GrantFiled: March 4, 2013Date of Patent: November 17, 2015Assignee: Intel CorporationInventors: Xiuting C. Man, Michael N. Derr, Jay D. Schwartz, Stephen H. Gunther, Jeremy J. Shrall, Shaun M. Conrad, Avinash N. Ananthakrishnan
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Publication number: 20150241949Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.Type: ApplicationFiled: April 27, 2015Publication date: August 27, 2015Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Publication number: 20150185797Abstract: Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.Type: ApplicationFiled: December 28, 2013Publication date: July 2, 2015Inventors: Lawrence A. Cooper, Justin J. Song, Xiuting C. Man, Nagi Aboulenein, Christopher E. Cox, Rebecca Z. Loop
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Patent number: 9063727Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.Type: GrantFiled: August 31, 2012Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Xiuting C. Man, Michael N. Derr, Jay D. Schwartz, Stephen H. Gunther, Jeremy J. Shrall, Shaun M. Conrad, Avinash N. Ananthakrishan
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Patent number: 9037840Abstract: An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.Type: GrantFiled: June 29, 2012Date of Patent: May 19, 2015Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Publication number: 20140089688Abstract: In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to the first domain and having at least one non-core circuit, and a power control unit (PCU) coupled to the first and second domains. The PCU may include a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information. Other embodiments are described and claimed.Type: ApplicationFiled: September 27, 2012Publication date: March 27, 2014Inventors: Xiuting C. Man, Avinash N. Ananthakrishnan, Michael N. Derr, Craig Forbell
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Publication number: 20140068293Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.Type: ApplicationFiled: March 4, 2013Publication date: March 6, 2014Inventors: Xiuting C. Man, Michael N. Derr, Jay D. Schwartz, Stephen H. Gunther, Jeremy J. Shrall, Shaun M. Conrad, Avinash N. Ananthakrishnan
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Publication number: 20140006761Abstract: An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
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Patent number: 6412901Abstract: A monitoring system monitors a pressure wave developed in the surrounding ambient environment during inkjet droplet formation. The monitoring system uses either acoustic, ultrasonic, or other pressure wave monitoring mechanisms, such as a laser vibrometer, an ultrasonic transducer, or an accelerometer sensor, for instance, a microphone to detect droplet formation. One sensor is incorporated in the printhead itself, while others may be located externally. The monitoring system generates information used to determine current levels of printhead performance, to which the printer may respond by adjusting print modes, servicing the printhead, adjusting droplet formation, or by providing an early warning before an inkjet cartridge is completely empty. During printhead manufacturing, an array of such sensors may be used in quality assurance to determine printhead performance. An inkjet printing mechanism is also equipped for using this monitoring system, and a monitoring method is also provided.Type: GrantFiled: April 24, 2001Date of Patent: July 2, 2002Assignee: Hewlett-Packard CompanyInventors: Wen-Li Su, Trudy L. Benjamin, Steven B. Elgee, Thomas F. Uhling, Bruce A. Axten, Kerry J. Lundsten, Xiuting C. Man, Tamara L. Hahn, Michael T. Dangelo, Bryan D. Woll, Timothy L. Weber, James W Pearson, Iue-Shuenn Chen
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Publication number: 20010028371Abstract: A monitoring system monitors a pressure wave developed in the surrounding ambient environment during inkjet droplet formation. The monitoring system uses either acoustic, ultrasonic, or other pressure wave monitoring mechanisms, such as a laser vibrometer, an ultrasonic transducer, or an accelerometer sensor, for instance, a microphone to detect droplet formation. One sensor is incorporated in the printhead itself, while others may be located externally. The monitoring system generates information used to determine current levels of printhead performance, to which the printer may respond by adjusting print modes, servicing the printhead, adjusting droplet formation, or by providing an early warning before an inkjet cartridge is completely empty. During printhead manufacturing, an array of such sensors may be used in quality assurance to determine printhead performance. An inkjet printing mechanism is also equipped for using this monitoring system, and a monitoring method is also provided.Type: ApplicationFiled: April 24, 2001Publication date: October 11, 2001Inventors: Wen-LI Su, Trudy L. Benjamin, Steven B. Elgee, Thomas F. Uhling, Bruce A. Axten, Kerry J. Lundsten, Xiuting C. Man, Tamara L. Hahn, Michael T. Dangelo, Bryan D. Woll, Timothy L. Weber, James W. Pearson, Iue-Shuenn Chen