Abstract: A shift register and a display panel. The shift register includes an output adjustment module, a trigger write module, and a node adjustment module. A first terminal of the output adjustment module inputs a first clock signal. A second terminal of the output adjustment module inputs a first power signal. The output adjustment module is configured to adjust the shift register to output the first clock signal or the first power signal according to the signal on a first control node and the signal on a second control node of the output adjustment module. The trigger write module is configured to write a trigger signal to the second control node according to the clock signal of the control terminal of the trigger write module. The node adjustment module is configured to adjust the signal on the first control node.

Abstract: A display panel includes a substrate; a first metal layer comprising a gate of a driving transistor; a second metal layer comprising a capacitor plate of a storage capacitor; a third metal layer, located on one side of the second metal layer away from the substrate and comprising a data line. An orthographic projection of the data line on the substrate is non-overlapped with the orthographic projection of the gate projected on the substrate; and a first shielding electrode, having a fixed potential. A part of the orthographic projection of the gate projected on the substrate is located in an orthographic projection of the first shielding electrode projected on the substrate, and the rest part of the orthographic projection of the gate projected on the substrate is located in the orthographic projection of the capacitor plate projected on the substrate.

Abstract: A display panel and a display device. The display panel includes a first area and a second area, and a plurality of first pixel rows and a plurality of second pixel rows, each of the first pixel row and the second pixel row includes a plurality of pixels. The number of the pixels of each first pixel row is greater than the number of the pixels of each second pixel row. The pixels in the first pixel row are display pixels, and the plurality of pixels in the second pixel row are display pixels and virtual pixels. The display pixel includes a display pixel circuit, the virtual pixel includes a virtual pixel circuit, and the virtual pixel circuit includes a compensation unit.

Abstract: A shift register and a display panel. The shift register includes an output adjustment module, a trigger write module, and a node adjustment module. A first terminal of the output adjustment module inputs a first clock signal. A second terminal of the output adjustment module inputs a first power signal. The output adjustment module is configured to adjust the shift register to output the first clock signal or the first power signal according to the signal on a first control node and the signal on a second control node of the output adjustment module. The trigger write module is configured to write a trigger signal to the second control node according to the clock signal of the control terminal of the trigger write module. The node adjustment module is configured to adjust the signal on the first control node.

Abstract: A display panel and a display device. The display panel includes a first area and a second area, and a plurality of first pixel rows and a plurality of second pixel rows, each of the first pixel row and the second pixel row includes a plurality of pixels. The number of the pixels of each first pixel row is greater than the number of the pixels of each second pixel row. The pixels in the first pixel row are display pixels, and the plurality of pixels in the second pixel row are display pixels and virtual pixels. The display pixel includes a display pixel circuit, the virtual pixel includes a virtual pixel circuit, and the virtual pixel circuit includes a compensation unit.

Abstract: The present application discloses an array substrate, a display panel, and a display apparatus. The array substrate includes a hole-punching area, a wiring area at least partially surrounding the hole-punching area and a wire-wrapping area between the hole-punching area and the wiring area, the array substrate includes: a substrate and a first wiring layer arranged on the substrate; a shielding assembly at least including a first shielding layer arranged on a side of the first wiring layer, the side of the first wiring layer being away from the substrate, and the first shielding layer being insulated from the first signal wires in the first wiring layer, the first shielding layer being electrically connected to a first fixed potential terminal, wherein an orthographic projection of the first shielding layer on the substrate covers an orthographic projection of the first wire-wrapping segment of the first signal wire on the substrate.

Abstract: A display panel includes a substrate; a first metal layer comprising a gate of a driving transistor; a second metal layer comprising a capacitor plate of a storage capacitor; a third metal layer, located on one side of the second metal layer away from the substrate and comprising a data line. An orthographic projection of the data line on the substrate is non-overlapped with the orthographic projection of the gate projected on the substrate; and a first shielding electrode, having a fixed potential. A part of the orthographic projection of the gate projected on the substrate is located in an orthographic projection of the first shielding electrode projected on the substrate, and the rest part of the orthographic projection of the gate projected on the substrate is located in the orthographic projection of the capacitor plate projected on the substrate.

Abstract: The present application provides a display panel and a driving method of a pixel circuit. The display panel includes a scan driver, a light-emitting control driver, a data driver, a plurality of pixel circuits, and a plurality of pixels each corresponding to one of the pixel circuits. Each of the pixel circuits includes a first transistor to a seventh transistor, a capacitor and an organic light-emitting diode. A control terminal of the fourth transistor is configured to input a first scanning signal; and a first electrode of the fourth transistor is connected to a second electrode of the third transistor, a control terminal of the first transistor and a terminal of the capacitor. Another terminal of the capacitor is connected to a first electrode of a fifth transistor. A second electrode of the fourth transistor is configured to input a first reference voltage.

Abstract: The present application provides a display panel and a driving method of a pixel circuit. The display panel includes a scan driver, a light-emitting control driver, a data driver, a plurality of pixel circuits, and a plurality of pixels each corresponding to one of the pixel circuits. Each of the pixel circuits includes a first transistor to a seventh transistor, a capacitor and an organic light-emitting diode. A control terminal of the fourth transistor is configured to input a first scanning signal; and a first electrode of the fourth transistor is connected to a second electrode of the third transistor, a control terminal of the first transistor and a terminal of the capacitor. Another terminal of the capacitor is connected to a first electrode of a fifth transistor. A second electrode of the fourth transistor is configured to input a first reference voltage.