Patents by Inventor Xiyuan Wu

Xiyuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Computer implemented system and method of translation of verification commands of an electronic design
    Patent number: 11704448
    Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: July 18, 2023
    Assignee: ZIPALOG, INC.
    Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
  • COMPUTER IMPLEMENTED SYSTEM AND METHOD OF TRANSLATION OF VERIFICATION COMMANDS OF AN ELECTRONIC DESIGN
    Publication number: 20210357539
    Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 18, 2021
    Inventors: Felicia James, Michael Krasnicki, Xiyuan WU
  • Computer implemented system and method of translation of verification commands of an electronic design
    Patent number: 11074373
    Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: July 27, 2021
    Assignee: Zipalog Inc.
    Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
  • COMPUTER IMPLEMENTED SYSTEM AND METHOD OF TRANSLATION OF VERIFICATION COMMANDS OF AN ELECTRONIC DESIGN
    Publication number: 20200242277
    Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventors: Felicia James, Michael Krasnicki, Xiyuan WU
  • Computer implemented system and method of translation of verification commands of an electronic design
    Patent number: 10621290
    Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, a first stimulus parameter of the at least two stimulus parameters comprising an input to an input pin of the electronic circuit defined by the electronic design file, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least two stimulus parameter stored in at least one specification database and at least one measurement parameter st
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 14, 2020
    Assignee: ZIPALOG, INC.
    Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
  • COMPUTER IMPLEMENTED SYSTEM AND METHOD OF TRANSLATION OF VERIFICATION COMMANDS OF AN ELECTRONIC DESIGN
    Publication number: 20190362032
    Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, a first stimulus parameter of the at least two stimulus parameters comprising an input to an input pin of the electronic circuit defined by the electronic design file, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least two stimulus parameter stored in at least one specification database and at least one measurement parameter st
    Type: Application
    Filed: August 9, 2019
    Publication date: November 28, 2019
    Inventors: FELICIA JAMES, MICHAEL KRASNICKI, XIYUAN WU
  • Computer implemented system and method of translation of verification commands of an electronic design
    Patent number: 10402505
    Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netl
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 3, 2019
    Assignee: ZIPALOG, INC.
    Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
  • COMPUTER IMPLEMENTED SYSTEM AND METHOD OF TRANSLATION OF VERIFICATION COMMANDS OF AN ELECTRONIC DESIGN
    Publication number: 20170316137
    Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netl
    Type: Application
    Filed: July 19, 2017
    Publication date: November 2, 2017
    Inventors: FELICIA JAMES, MICHAEL KRASNICKI, XIYUAN WU
  • Computer implemented system and method of translation of verification commands of an electronic design
    Patent number: 9715566
    Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: July 25, 2017
    Assignee: Zipalog, Inc.
    Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
  • COMPUTER IMPLEMENTED SYSTEM AND METHOD OF TRANSLATION OF VERIFICATION COMMANDS OF AN ELECTRONIC DESIGN
    Publication number: 20150324505
    Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.
    Type: Application
    Filed: May 8, 2015
    Publication date: November 12, 2015
    Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu