Patents by Inventor Xizeng(Stone) Shi

Xizeng(Stone) Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7110289
    Abstract: In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: September 19, 2006
    Assignees: Western Digital (Fremont), Inc., STMicroelectronics S.R.L.
    Inventors: Kyusik Sin, Hugh Craig Hiner, Xizeng (Stone) Shi, William D. Jensen, Hua-Ching Tong, Matthew R Gibbons, Roberto Bez, Giulio Casagrande, Paolo Cappeletti, Marco Pasotti
  • Patent number: 7012832
    Abstract: A magnetic random access memory (MRAM) device has increased ?R/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying resistance during reading, increasing ?R/R. The plural transistors can share a source region.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: March 14, 2006
    Assignees: WEstern Digital (Fremont), Inc., STMicroelectronics, S.r.I.
    Inventors: Kyusik Sin, Matthew R. Gibbons, William D. Jensen, Hugh Craig Hiner, Xizeng Stone Shi, Roberto Bez, Giulio Casagrande, Paolo Cappelletti
  • Patent number: 6873547
    Abstract: A magnetic memory is disclosed. The magnetic memory includes a first magnetic tunneling junction and a reference magnetic tunneling junction. The first magnetic tunneling junction includes a first ferromagnetic layer, a second ferromagnetic layer and a first insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The reference magnetic tunneling junction includes a third ferromagnetic layer, a fourth ferromagnetic layer and a second insulating layer between the third ferromagnetic layer and the fourth ferromagnetic layer. The magnetic memory also includes means for comparing a first output of the first magnetic tunneling junction with a reference output of the reference magnetic tunneling junction.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: March 29, 2005
    Assignee: Read Rite Corporation
    Inventors: Xizeng(Stone) Shi, Hua-Ching Tong, Aric K. Menon
  • Patent number: 6829160
    Abstract: A magnetic random access memory (MRAM) cell and a memory array formed from the MRAM cells are disclosed. The MRAM cell includes a magnetic tunneling junction and a transistor. The magnetic tunneling junction includes a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The gate of the transistor is coupled to a first end of the magnetic tunneling junction. The source of the transistor is coupled to a second end the magnetic tunneling junction. The drain of the transistor is coupled with an output for reading the magnetic memory cell. During reading, a read current is applied to the magnetic tunneling junction and the transistor is preferably operated in a saturation region.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: December 7, 2004
    Assignee: Western Digital (Fremont), Inc.
    Inventors: Quiqun (Kevin) Qi, Xizeng (Stone) Shi, Matthew Gibbons