Abstract: A system-in-package (SiP) system-integration integrated circuit (IC) chip package and a manufacturing method thereof are provided. The package includes a substrate, a passive device and two IC chips are provided on the substrate, an adhesive film is disposed between each of the two IC chips and the substrate, the IC chips are connected to first pads on the substrate through bonding wires, and the substrate is covered by a mold cap. A third IC chip may be further disposed on one of the IC chips, and the third IC chip is connected to the first pad and the IC chip under the third IC chip respectively through a bonding wire. A substrate adopting a surface mount technology (SMT) PAD window-opening manner is used, chip mounting is performed on the substrate, and the substrate undergoes reflow soldering, cleaning, die bonding, plasma cleaning, bonding, marking, cutting, and packing, so that the SiP system-integration IC chip package is manufactured.

Abstract: A dense-pitch small-pad copper wire bonded double IC chip stack package comprises a plastic package body, in which a lead frame carrier and a frame lead inner pin are arranged; the upper surface of the lead frame carrier is fixedly connected with a first IC chip; a second IC chip is stacked on the first IC chip; the upper surface of the first IC chip and the upper surface of the second IC chip are respectively provided with a plurality of pads which are arranged as two lines of pad groups in parallel; the two pad groups are respectively a first pad group and a second pad group; a metal ball is implanted on each pad; each metal ball is connected with a first copper bonding ball; and a third copper bonding wire is formed by looping and arching on a corresponding metal ball between the second IC chip and the first IC chip.

Abstract: A dense-pitch small-pad copper wire bonded double IC chip stack package comprises a plastic package body, in which a lead frame carrier and a frame lead inner pin are arranged; the upper surface of the lead frame carrier is fixedly connected with a first IC chip; a second IC chip is stacked on the first IC chip; the upper surface of the first IC chip and the upper surface of the second IC chip are respectively provided with a plurality of pads which are arranged as two lines of pad groups in parallel; the two pad groups are respectively a first pad group and a second pad group; a metal ball is implanted on each pad; each metal ball is connected with a first copper bonding ball; and a third copper bonding wire is formed by looping and arching on a corresponding metal ball between the second IC chip and the first IC chip.

Abstract: A system-in-package (SiP) system-integration integrated circuit (IC) chip package and a manufacturing method thereof are provided. The package includes a substrate, a passive device and two IC chips are provided on the substrate, an adhesive film is disposed between each of the two IC chips and the substrate, the IC chips are connected to first pads on the substrate through bonding wires, and the substrate is covered by a mold cap. A third IC chip may be further disposed on one of the IC chips, and the third IC chip is connected to the first pad and the IC chip under the third IC chip respectively through a bonding wire. A substrate adopting a surface mount technology (SMT) PAD window-opening manner is used, chip mounting is performed on the substrate, and the substrate undergoes reflow soldering, cleaning, die bonding, plasma cleaning, bonding, marking, cutting, and packing, so that the SiP system-integration IC chip package is manufactured.