Patents by Inventor Xizhu Peng

Xizhu Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Output control circuit, method for transmitting data and electronic device
    Patent number: 11483010
    Abstract: An output control circuit, a method for transmitting data, and an electronic device are disclosed. The output control circuit includes: a serial-to-parallel conversion circuit configured to obtain at least one group of parallel data through a serial-to-parallel conversion; an intermediate-stage cache circuit configured to divide the at least one group of parallel data into at least two categories of subgroup parallel data according to sequence of serial-to-parallel conversion; a latch output circuit including a plurality of latch arrays each of which receiving any category of subgroup parallel data and latching and outputting any subgroup parallel data in any category of subgroup parallel data; and a selection control circuit configured to, within an effective pulse duration of the any subgroup parallel data, control a latch array for the any subgroup parallel data in the plurality of latch arrays to latch and output the any subgroup parallel data.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: October 25, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Junrui Zhang, Xuehui Zhu, Ronghua Lan, Xin Xiang, Xiaoqiao Liu, Xizhu Peng, He Tang
  • OUTPUT CONTROL CIRCUIT, METHOD FOR TRANSMITTING DATA AND ELECTRONIC DEVICE
    Publication number: 20210152184
    Abstract: An output control circuit, a method for transmitting data, and an electronic device are disclosed. The output control circuit includes: a serial-to-parallel conversion circuit configured to obtain at least one group of parallel data through a serial-to-parallel conversion; an intermediate-stage cache circuit configured to divide the at least one group of parallel data into at least two categories of subgroup parallel data according to sequence of serial-to-parallel conversion; a latch output circuit including a plurality of latch arrays each of which receiving any category of subgroup parallel data and latching and outputting any subgroup parallel data in any category of subgroup parallel data; and a selection control circuit configured to, within an effective pulse duration of the any subgroup parallel data, control a latch array for the any subgroup parallel data in the plurality of latch arrays to latch and output the any subgroup parallel data.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 20, 2021
    Inventors: Junrui Zhang, Xuehui Zhu, Ronghua Lan, Xin Xiang, Xiaoqiao Liu, Xizhu Peng, He Tang