Abstract: A method for predicting mass of heavy vehicles based on networked operating data and machine learning includes: collecting operating data; extracting speed, engine output torque, satellite elevation, and gear position under a driving condition; determining a transmission ratio of the heavy vehicle based on the gear position; filtering the speed, engine output torque, and the satellite elevation using three of the plurality of filtering parameters; determining a filtered vehicle longitudinal acceleration under the driving condition using the filtered speed, and one of the plurality of filtering parameters; determining a filtered road gradient sine value under the driving condition using the filtered speed, satellite elevation, and one of the plurality of filtering parameters; and inputting the speed, engine output torque, vehicle longitudinal acceleration, road gradient sine value, and transmission ratio into a vehicle mass prediction model to obtain a predicted mass.

Abstract: An avatar method, apparatus and device, and a medium are provided. The method includes: acquiring a target image in response to a user input; and obtaining an avatar corresponding to the target image by using a first generator; the first generator being trained and obtained on the basis of a first sample image set and a second sample image set generated by a three-dimensional model. In the present disclosure, by using the first generator, the generation method for an avatar is effectively simplified, thus improving generation efficiency, and avatars in one-to-one correspondence to target image can be generated, so that the avatars are more diversified. Additionally, the first generator is easy to deploy in various production environments, thus reducing the performance requirements on hardware devices.

Abstract: A dynamic impedance imaging system includes a dynamic impedance imaging sensor, an impedance detection and flow rate measurement module and an electrical impedance tomography (EIT) instrument. The impedance detection and flow rate measurement module is configured to detect an abnormal particle flowing through the dynamic impedance imaging sensor to obtain a flow rate of the abnormal particle, and generate a synchronous trigger signal. The EIT instrument is configured to inject a sinusoidal excitation current into the dynamic impedance imaging sensor under the trigger of the synchronous trigger signal, perform multi-channel interleaved sampling for the abnormal particle according to the flow rate to acquire multi-channel sampled data, and calibrate the multi-channel sampled data to implement impedance tomography imaging for the abnormal particle.

Abstract: A vortex-induced vibration power generation device with a magnetic boundary structure, including upper and lower opposite groups of fixed sleeves. Each fixed sleeve includes two vertical sleeves. The vertical sleeves are hollow cavities, and include sealed ends and open ends. Rotating magnetic poles are arranged in the sealed ends of the vertical sleeves. Coil slots are formed in the inner walls of the vertical sleeves. Coil windings are mounted in the coil slots. The vortex-induced vibration power generation device further includes linear bearings. The end portions of the linear bearings are fixedly connected with the open ends of the vertical sleeves through flanges. A vibration mechanism includes a vibration rod and vibration guide rods fixedly connected with the vibration rod. Magnetic coil mounting slots and anti-falling rings are arranged on the vibration guide rods. Magnetic coils are mounted in the magnetic coil mounting slots.

Abstract: An avatar method, apparatus and device, and a medium are provided. The method includes: acquiring a target image in response to a user input; and obtaining an avatar corresponding to the target image by using a first generator; the first generator being trained and obtained on the basis of a first sample image set and a second sample image set generated by a three-dimensional model. In the present disclosure, by using the first generator, the generation method for an avatar is effectively simplified, thus improving generation efficiency, and avatars in one-to-one correspondence to target image can be generated, so that the avatars are more diversified. Additionally, the first generator is easy to deploy in various production environments, thus reducing the performance requirements on hardware devices.

Abstract: A dynamic impedance imaging system includes a dynamic impedance imaging sensor, an impedance detection and flow rate measurement module and an electrical impedance tomography (EIT) instrument. The impedance detection and flow rate measurement module is configured to detect an abnormal particle flowing through the dynamic impedance imaging sensor to obtain a flow rate of the abnormal particle, and generate a synchronous trigger signal. The EIT instrument is configured to inject a sinusoidal excitation current into the dynamic impedance imaging sensor under the trigger of the synchronous trigger signal, perform multi-channel interleaved sampled for the abnormal particle according to the flow rate to acquire multi-channel sampled data, and calibrate the multi-channel sampled data to implement impedance tomography imaging for the abnormal particle.

Abstract: A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

Abstract: A vortex-induced vibration power generation device with a magnetic boundary structure, including upper and lower opposite groups of fixed sleeves. Each fixed sleeve includes two vertical sleeves. The vertical sleeves are hollow cavities, and include sealed ends and open ends. Rotating magnetic poles are arranged in the sealed ends of the vertical sleeves. Coil slots are formed in the inner walls of the vertical sleeves. Coil windings are mounted in the coil slots. The vortex-induced vibration power generation device further includes linear bearings. The end portions of the linear bearings are fixedly connected with the open ends of the vertical sleeves through flanges. A vibration mechanism includes a vibration rod and vibration guide rods fixedly connected with the vibration rod. Magnetic coil mounting slots and anti-falling rings are arranged on the vibration guide rods. Magnetic coils are mounted in the magnetic coil mounting slots.

Abstract: In order to eliminate an increase in the source potential of a transistor selected during writing or reading, this semiconductor device is equipped with: a variable-resistance type first switch having a first terminal and a second terminal; a variable-resistance type second switch having a third terminal and a fourth terminal, the third terminal being connected to the second terminal to form an intermediate node; first wiring connected to the first terminal; second wiring connected to the fourth terminal and, in a planar view, extending in a direction crossing the first wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first well terminal connection line to which a well terminal of the first selection transistor is connected; and a second well terminal connection line to which a well terminal of the second selection transistor is connected.

Abstract: A reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly includes: a first non-volatile resistive switch; and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

Abstract: A design assistance system according to the present invention assists in designing a circuit to be mounted on a programmable logic integrated circuit including a resistance change element. The design assistance system includes: a memory; and at least one processor coupled to the memory. The processor performs operations. The operations includes: generating rewriting history information indicating a number (count) of changing times of a state of the resistance change element; calculating an abrasion cost of a switch included in the circuit, based on the rewriting history information; and carrying out wiring of the circuit, based on an evaluation function including the abrasion cost.

Abstract: A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.

Abstract: A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

Abstract: A reconfigurable circuit includes: a complementary resistive switch including a first resistive switch, a second resistive switch and a selection transistor, wherein a first terminal of the first resistive switch is connected to a first terminal of the second resistive switch and connected to a first terminal of the selection transistor; a first current source having a first terminal connected to a second terminal of the first resistive switch and a second terminal connected to a ground voltage line; a second current source having a first terminal connected to a second terminal of the second resistive switch and a second terminal connected to the ground voltage line; and a resistor having a first terminal connected to a second terminal of the selection transistor and a second terminal connected to a power voltage line.

Abstract: A reconfigurable circuit includes: a plurality of first lines; one or more second lines; a non-volatile resistive cell coupling one of the first lines with one of the second lines at each cross-point between the first lines and the second lines; and first switch elements including first terminals respectively coupled to the first lines, wherein each of the first switch elements is separately turned on or off in accordance with a control signal applied thereto.

Abstract: A semiconductor device which includes: a switch array in which a switch cell including a variable resistance switch is arranged at each location where a plurality of wires constituting a crossbar switch intersect; a first selection circuit that selects all of the variable resistance switches included in the switch array; a second selection circuit that selects any of the variable resistance switches included in the switch array; a reading circuit that reads a state of the variable resistance switch selected by any of the first selection circuit and the second selection circuit; and an error detection circuit that detects, based on a state of the variable resistance switch read by the reading circuit, an error in at least any of the variable resistance switches included in the switch array.

Abstract: A design assistance system including: a logic synthesis unit that receives input of an operation description file of the programmable logic integrated circuit, logically synthesizes the inputted operation description file, and generates a net list by using logic elements included in the programmable logic integrated circuit; an arrangement wiring unit that generates resource information of the programmable logic integrated circuit, arranges the logic elements included in the net list on the basis of the generated resource information, and virtually generates a signal path by laying wires among the arranged logic elements; and a reliability control unit that generates configuration information of the programmable logic integrated circuit on the basis of at least two reliability modes, and outputs the generated configuration information.

Abstract: A reconfigurable circuit comprising: crossbar switches; wires, each of which is coupled to one output port of one crossbar switch and input ports of the other crossbar switches; at least one inverter inserted on each wire for driving long-distance signal transfer, wherein one or less first inverter is inserted on the wire between two adjacent crossbar switches; one or two second inverters inserted between a crossbar switch input port and its connected wire.

Abstract: A semiconductor device includes: first wires which extend in a first direction; second wires extending in a second direction; a unit element which comprises two variable resistance elements connected in series, and has one end connected to a first wire and the other end connected to a second wire; a first control line for controlling the supply of a voltage to the first wire; a second control line for controlling the supply of a voltage to the second wire; and a cell circuit connected to an intermediate node between the two variable resistance elements and also connected to the first control line and the second control line. The cell circuit has: a cell transistor connected to an intermediate node writing driver which supplies a voltage to the intermediate node; and a cell control circuit which controls an electrical conduction state of the cell transistor.

Abstract: A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.