Abstract: An apparatus for power management of a device includes a processing system including one or more processors and one or more memories coupled to the one or more processors. The processing system is configured to receive power usage information associated with the device and to receive a battery power availability (BPA) indication associated with a battery of the device. The processing system is further configured to adjust, based on the power usage information and the BPA indication, a power allocation associated with the device to enable operation of the device based on a peak power consumption level. The peak power consumption level is less than a threshold power consumption level that is associated with power consumption throttling of one or more components of the device.

Abstract: An apparatus is disclosed for providing frequency stabilization. The apparatus includes a first supply voltage node, a second supply voltage node, an oscillator circuit coupled to the first supply voltage node, at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, and at least one load circuit. The at least one clock buffer is configured to selectively be in a disabled state or an enabled state to pass the clock signal to at least one client of multiple clients. The at least one load circuit includes an input coupled to the output of the oscillator circuit. The at least one load circuit also includes an output configured to be coupled to a ground. The at least one load circuit is configured to be connected to the first supply voltage node for at least a portion of time.

Abstract: An apparatus is disclosed for providing frequency stabilization. The apparatus includes a first supply voltage node, a second supply voltage node, an oscillator circuit coupled to the first supply voltage node, at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, and at least one load circuit. The at least one clock buffer is configured to selectively be in a disabled state or an enabled state to pass the clock signal to at least one client of multiple clients. The at least one load circuit includes an input coupled to the output of the oscillator circuit. The at least one load circuit also includes an output configured to be coupled to a ground. The at least one load circuit is configured to be connected to the first supply voltage node for at least a portion of time.

Abstract: Methods, systems, and devices for wireless communication in a user equipment (UE) are described in which a cycle duration of an extended discontinuous reception (eDRX) cycle is determined. The UE enters a sleep state of the eDRX cycle and, based on the determination of the cycle duration, uses a first clock as a timer during the sleep state and uses a second clock as a timing calibrator during the sleep state. The first clock may have a lower power consumption and a higher frequency error, and the second clock may have a higher power consumption and a lower frequency error.

Abstract: Various embodiments of methods and systems for closed loop multimode sleep clock frequency compensation in a portable computing device are disclosed. An exemplary embodiment leverages a modem to determine a frequency shift on a sleep clock signal when a reference clock has transitioned into a power saving mode. Using the frequency shift calculation, a compensation capacitor may be adjusted to deliver a more optimum dummy load on the crystal oscillator when the reference clock is taken offline. The method may iterate through until the actual frequency shift of the sleep clock is within an acceptable tolerance relative to zero and, further, may also set a status bit to indicate that the sleep clock frequency is stable.