Patents by Inventor Xusheng Wu
Xusheng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948998Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.Type: GrantFiled: July 28, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Xusheng Wu, Chang-Miao Liu, Huiling Shang
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Publication number: 20240105517Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Xusheng Wu, Ying-Keung Leung, Huiling Shang
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Publication number: 20240096971Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Xusheng WU, Chang-Miao LIU, Ying-Keung LEUNG, Huiling SHANG, Youbo LIN
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Patent number: 11935954Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.Type: GrantFiled: July 30, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu, Chien-Tai Chan
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Patent number: 11916105Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.Type: GrantFiled: March 26, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bwo-Ning Chen, Xusheng Wu, Pin-Ju Liang, Chang-Miao Liu, Shih-Hao Lin
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Patent number: 11855155Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.Type: GrantFiled: April 11, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Xusheng Wu, Chang-Miao Liu, Ying-Keung Leung, Huiling Shang, Youbo Lin
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Patent number: 11854896Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.Type: GrantFiled: March 26, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Xusheng Wu, Ying-Keung Leung, Huiling Shang
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Patent number: 11837662Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.Type: GrantFiled: December 15, 2020Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Xusheng Wu, Chang-Miao Liu, Huiling Shang
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Publication number: 20230387300Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Xusheng Wu, Chang-Miao Liu, Huiling Shang
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Publication number: 20230387199Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Bwo-Ning Chen, Xusheng Wu, Pin-Ju Liang, Chang-Miao Liu, Shih-Hao Lin
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Publication number: 20230378321Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.Type: ApplicationFiled: July 27, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xusheng WU, Chang-Miao LIU, Huiling SHANG
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Publication number: 20230369128Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Wei-Lun Min, Xusheng Wu, Chang-Miao Liu
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Patent number: 11769819Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a metal gate stack over the semiconductor substrate. The semiconductor device structure also includes a spacer element over a sidewall of the metal gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. An atomic concentration of the dopant decreases along a direction from an inner surface of the spacer element adjacent to the metal gate stack towards an outer surface of the spacer element.Type: GrantFiled: December 28, 2020Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xusheng Wu, Chang-Miao Liu, Huiling Shang
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Patent number: 11756835Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.Type: GrantFiled: July 11, 2022Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Lun Min, Xusheng Wu, Chang-Miao Liu
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Patent number: 11728405Abstract: A semiconductor structure includes source/drain (S/D) features disposed over a semiconductor substrate, a metal gate stack disposed between the S/D features, where the metal gate stack traverses a channel region between the S/D features, gate spacers disposed on sidewalls of the metal gate stack, and an etch-stop layer (ESL) disposed over the gate spacers and the S/D features. The semiconductor structure further includes an oxide liner disposed on the ESL, where the oxide liner includes silicon oxide and silicon dioxide, and an interlayer dielectric (ILD) layer disposed on the oxide liner, where composition of the ILD layer is different from composition of the oxide liner.Type: GrantFiled: March 16, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu, Shih-Hao Lin
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Patent number: 11621350Abstract: A semiconductor structure includes a gate stack on a semiconductor substrate and an etch stop layer disposed on the gate stack and the semiconductor substrate. The etch stop layer includes a first portion disposed on sidewalls of the gate stack and a second portion disposed on a top surface of the semiconductor substrate within a source/drain region. The semiconductor structure further includes a dielectric stress layer disposed on the second portion of the etch stop layer and being free from the first portion of the etch stop layer other than at a corner area formed by the first portion intersecting the second portion. The dielectric stress layer is different from the etch stop layer in composition and is configured to apply a compressive stress to a channel region underlying the gate stack.Type: GrantFiled: August 16, 2021Date of Patent: April 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Xusheng Wu, Youbo Lin
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Publication number: 20230060786Abstract: A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first portion of an oxide layer around the dummy contact structure, performing a second etching process to at least partially remove the first portion of oxide layer, forming a spacer layer around the dummy contact structure, performing a second deposition process to form a second portion of the oxide layer around the spacer layer, removing the spacer layer and the dummy contract structure to leave an opening, and filling the opening with a conductive material to form a conductive plug.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Bwo-Ning Chen, Xusheng Wu, Yin-Pin Wang, Yuh-Sheng Jean, Chang-Miao Liu
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Publication number: 20230035791Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bwo-Ning CHEN, Xusheng WU, Chang-Miao LIU, Chien-Tai CHAN
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Publication number: 20220367684Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Xusheng WU, Chang-Miao LIU, Huiling SHANG
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Publication number: 20220367685Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Xusheng WU, Chang-Miao LIU, Huiling SHANG