Patents by Inventor Xuan Anh TRAN
Xuan Anh TRAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929205Abstract: The invention offers an ultracapacitor-based power system solution with four main functional blocks which are power conditioning block, monitoring block, charge-discharge block and protection block. The proposed system has the advantage of working well in the environment of vibration, high temperature, has a large capacity to provide a large amount and radiates less heat compared to systems using traditional batteries. In addition, the system has functions to protect and stabilize the output voltage, and the operating parameters of the system is monitored continuously.Type: GrantFiled: May 10, 2021Date of Patent: March 12, 2024Assignee: VIETTEL GROUPInventors: Truong Giang Duong, Canh Duong Nguyen, Duc Anh Nguyen, Xuan Chien Vuong, Phuong Nam Tran
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Patent number: 11894078Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.Type: GrantFiled: May 26, 2022Date of Patent: February 6, 2024Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Xuan-Anh Tran, Jessica Chen, Jason A. Durand, Nevil N. Gajera, Yen Chun Lee
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Publication number: 20230267996Abstract: Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Inventors: Lingming Yang, Xuan Anh Tran, Karthik Sarpatwari, Francesco Douglas Verna-Ketel, Jessica Chen, Nevil N. Gajera, Amitava Majumdar
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Patent number: 11694747Abstract: Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.Type: GrantFiled: June 3, 2021Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Lingming Yang, Xuan Anh Tran, Karthik Sarpatwari, Francesco Douglas Verna-Ketel, Jessica Chen, Nevil N. Gajera, Amitava Majumdar
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Patent number: 11568952Abstract: Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.Type: GrantFiled: June 2, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Xuan-Anh Tran, Nevil N. Gajera, Karthik Sarpatwari, Amitava Majumdar
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Publication number: 20220392526Abstract: Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.Type: ApplicationFiled: June 3, 2021Publication date: December 8, 2022Inventors: Lingming Yang, Xuan Anh Tran, Karthik Sarpatwari, Francesco Douglas Verna-Ketel, Jessica Chen, Nevil N. Gajera, Amitava Majumdar
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Publication number: 20220392560Abstract: Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.Type: ApplicationFiled: June 2, 2021Publication date: December 8, 2022Inventors: Xuan-Anh Tran, Nevil N. Gajera, Karthik Sarpatwari, Amitava Majumdar
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Patent number: 11515205Abstract: One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.Type: GrantFiled: August 30, 2019Date of Patent: November 29, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Eswar Ramanathan, Sunil Kumar Singh, Xuan Anh Tran, Suryanarayana Kalaga, Juan Boon Tan
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Publication number: 20220284973Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.Type: ApplicationFiled: May 26, 2022Publication date: September 8, 2022Inventors: Karthik Sarpatwari, Xuan-Anh Tran, Jessica Chen, Jason A. Durand, Nevil N. Gajera, Yen Chun Lee
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Publication number: 20220271090Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.Type: ApplicationFiled: May 12, 2022Publication date: August 25, 2022Inventors: Sunil Kumar SINGH, Xuan Anh TRAN, Eswar RAMANATHAN, Suryanarayana KALAGA, Craig M. CHILD, Robert FOX
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Patent number: 11367750Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.Type: GrantFiled: June 12, 2019Date of Patent: June 21, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Sunil Kumar Singh, Xuan Anh Tran, Eswar Ramanathan, Suryanarayana Kalaga, Craig M. Child, Robert Fox
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Patent number: 11355209Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.Type: GrantFiled: July 10, 2020Date of Patent: June 7, 2022Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Xuan-Anh Tran, Jessica Chen, Jason A. Durand, Nevil N. Gajera, Yen Chun Lee
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Publication number: 20220013183Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Inventors: Karthik Sarpatwari, Xuan-Anh Tran, Jessica Chen, Jason A. Durand, Nevil N. Gajera, Yen Chun Lee
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Patent number: 11094585Abstract: One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.Type: GrantFiled: July 8, 2019Date of Patent: August 17, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Xuan Anh Tran, Eswar Ramanathan, Sunil Kumar Singh, Suryanarayana Kalaga, Suresh Kumar Regonda, Juan Boon Tan
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Publication number: 20210066126Abstract: One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.Type: ApplicationFiled: August 30, 2019Publication date: March 4, 2021Inventors: Eswar Ramanathan, Sunil Kumar Singh, Xuan Anh Tran, Suryanarayana Kalaga, Juan Boon Tan
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Publication number: 20210013095Abstract: One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.Type: ApplicationFiled: July 8, 2019Publication date: January 14, 2021Inventors: Xuan Anh Tran, Eswar Ramanathan, Sunil Kumar Singh, Suryanarayana Kalaga, Suresh Kumar Regonda, Juan Boon Tan
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Patent number: 10886287Abstract: One illustrative MPT device disclosed herein includes an active region and an inactive region, isolation material positioned between the active region and the inactive region, the isolation material electrically isolating the active region from the inactive region, and an FG MTP cell formed in the active region. In this example, the FG MTP cell includes a floating gate, wherein first, second and third portions of the floating gate are positioned above the active region, the inactive region and the isolation material, respectively, and a control gate positioned above at least a portion of the inactive region, wherein the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate.Type: GrantFiled: January 14, 2019Date of Patent: January 5, 2021Assignee: GLOBALFOUNDRIES INC.Inventors: Xuan Anh Tran, Sunil Kumar Singh, Shyue Seng Tan
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Publication number: 20200395541Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.Type: ApplicationFiled: June 12, 2019Publication date: December 17, 2020Inventors: Sunil Kumar SINGH, Xuan Anh TRAN, Eswar RAMANATHAN, Suryanarayana KALAGA, Craig M. CHILD, Robert FOX
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Patent number: 10804323Abstract: Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.Type: GrantFiled: December 17, 2018Date of Patent: October 13, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Xuan Anh Tran, Eng Huat Toh, Shyue Seng Tan, Yuan Sun, Elgin Kiok Boone Quek
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Publication number: 20200227424Abstract: One illustrative MPT device disclosed herein includes an active region and an inactive region, isolation material positioned between the active region and the inactive region, the isolation material electrically isolating the active region from the inactive region, and an FG MTP cell formed in the active region. In this example, the FG MTP cell includes a floating gate, wherein first, second and third portions of the floating gate are positioned above the active region, the inactive region and the isolation material, respectively, and a control gate positioned above at least a portion of the inactive region, wherein the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate.Type: ApplicationFiled: January 14, 2019Publication date: July 16, 2020Inventors: Xuan Anh Tran, Sunil Kumar Singh, Shyue Seng Tan