Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A display device including a display panel is disclosed. The display panel includes a substrate, multiple scan lines, multiple data lines, multiple pixel structures, a first gate driving circuit, and a second gate driving circuit. The pixel structures are electrically connected to the scan lines and the data lines. Multiple first output stage circuits of the first gate driving circuit disposed in a peripheral area are electrically connected to the scan lines. Multiple second output stage circuits of the second gate driving circuit disposed in the peripheral area are electrically connected to the scan lines. A channel width of a first output transistor of the first output stage circuit is greater than a channel width of a second output transistor of the second output stage circuit.

Abstract: An automated dismantling and separation system for solar panels is provided, which mainly disassembles the aluminum frame of the solar panel to form the stack material through the frame disassembly system, and the stack material is transported by the handling device to the stack material disassembly system, and the stack material is heated through the heating unit to melt the EVA adhesive between the glass upper cover, wafer layer and backplane layer. Then the topmost material is removed through the suckers of the handling device to expose the residual adhesive, and the residual adhesive is scraped off by the scraper, so that each layer of material is repeatedly removed in sequence and collected and recycled respectively to achieve the purpose of high efficiency and environmental protection.

Abstract: This invention discloses a display panel includes a substrate and a sub-pixel. The sub-pixel is disposed on the substrate. The sub-pixel includes a transistor, and the transistor includes a gate, a semiconductor layer, a source, a drain, and a dummy electrode. The gate is disposed on the substrate. The semiconductor layer is disposed on the gate. The source and the drain are disposed on the semiconductor layer, the source is disposed at one end of the semiconductor layer, and the drain is disposed at the other end of the semiconductor layer. The dummy electrode is disposed on the semiconductor layer and between the source and the drain. The dummy electrode and the source are separated, the dummy electrode and the drain are separated, and the dummy electrode is electrically floating.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A display panel including a substrate, scan lines, data lines, pixel structures, and a light shielding pattern layer is provided. The substrate is provided with a display area. The scan lines and the data lines are disposed on the substrate, and intersect with each other. The pixel structures are disposed in the display area, and each includes a display transistor and a pixel electrode. The display transistor includes a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is disposed between the substrate and the first semiconductor pattern, and is electrically connected to one of the scan lines. The first source electrode is electrically connected to one of the data lines. The pixel electrode is electrically connected to the first drain electrode of the display transistor. The light shielding pattern layer is disposed between the first gate electrode and the substrate, and has a first opening overlapping the first gate electrode.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.

Abstract: A display panel includes a substrate, multiple scan lines, multiple data lines, and multiple pixel structures. The scan lines and the data lines are disposed on the substrate. The pixel structure is disposed on the substrate and electrically connected to the scan lines and the data lines, and includes an active device, a pixel electrode, a capacitor electrode, an overcoat layer, a first common electrode, a second common electrode, a first passivation layer, and a second passivation layer. The active device is electrically connected one scan line, one data line, and the pixel electrode. The capacitor electrode extends from a drain and is electrically connected to the pixel electrode. The overcoat layer is disposed between the pixel electrode and the capacitor electrode. The first common electrode overlaps the capacitor electrode, and is located between the overcoat layer and the capacitor electrode.

Abstract: A dual-medium TFB gasification incinerator and implementation method of a waste gasification incineration. The incinerator includes an incinerator body, a gas-solid separator, a waste heat recovery device, and an incinerator body support. The incinerator body includes a gasification section, a combustion section, and a heat exchange section that are all sequentially connected from bottom to top. The combustion section and the heat exchange section are indirectly connected. The incinerator body support includes at least one layer of transverse beam, which is located at a level higher than a connection part of the combustion section and faces the incinerator body. Each of the at least one layer of transverse beam is provided with a layer of support plate on a side close to the incinerator body. Each layer of support plate supports a first-stage of heat exchange furnace wall and heat conduction oil coil pipes provided on an inner surface of the first-stage.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: A photoelectric computing unit, a photoelectric computing array and a photoelectric computing method. The photoelectric computing unit includes a semiconductor multifunctional region structure, which includes at least one carrier control region, at least one coupling region, and at least one photon-generated carrier collection region and readout region.

Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a gate electrode, a gate electrode contact layer over the gate electrode, forming a dielectric layer over the gate electrode contact layer, and performing an etch through the dielectric layer, the etch forming an opening that exposes the gate electrode contact layer. The method further includes performing a post-etch treatment on the opening formed by the etch process by exposing the opening to a plasma. The method further includes forming gate electrode contacts in the openings after the post-etch treatment by a bottom-up deposition process.

Abstract: An edge assembly used for a plasma etching system is provided. The edge assembly includes: a focus ring peripherally surrounding an edge portion of a mounting platform mounted in the plasma etching system. The focus ring includes: a lower step portion proximate to the edge portion, the lower step portion extending vertically from a bottom surface of the focus ring to a lower step top surface; and an upper step portion distal to the edge portion, the upper step portion extending vertically from the bottom surface of the focus ring to an upper step top surface and extending radially from an upper step inner side to an upper step outer side. The focus ring is characterized by an air gap located in the upper step portion, and the air gap extends peripherally along a circumstance of the focus ring.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a silicon oxycarbonitride spacer, a silicon oxycarbide spacer, a silicon nitride spacer, and a source/drain structure. The gate structure is on the semiconductor substrate. The silicon oxycarbonitride spacer is on a sidewall of the gate structure. The silicon oxycarbide spacer is on a sidewall of the silicon oxycarbonitride spacer. The silicon nitride spacer is on a sidewall of the silicon oxycarbide spacer, in which an upper portion of the silicon nitride spacer has a lower density than a lower portion of the silicon nitride spacer. The source/drain structure is on the semiconductor substrate and adjacent to the gate structure.