Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.

Abstract: The present disclosure relates to methods and apparatuses for releasing a thin semiconductor substrate from a reusable template. The method involves forming a mechanically weak layer conformally on a semiconductor template. Then forming a thin semiconductor substrate conformally on the mechanically weak layer. The thin semiconductor substrate, the mechanically weak layer and the template forming a wafer. Then defining the border of the thin-film semiconductor substrate to be released by exposing the peripheral of the mechanically weak layer. Then releasing the thin-film semiconductor substrate by applying a controlled air flow parallel to said mechanically weak layer wherein the controlled air flow separates the thin semiconductor substrate and template according to lifting forces.

Abstract: A method for the fabrication of a three-dimensional thin-film semiconductor substrate with selective through-holes is provided. A porous semiconductor layer is conformally formed on a semiconductor template comprising a plurality of three-dimensional inverted pyramidal surface features defined by top surface areas aligned along a (100) crystallographic orientation plane of the semiconductor template and a plurality of inverted pyramidal cavities defined by sidewalls aligned along the (111) crystallographic orientation plane of the semiconductor template. An epitaxial semiconductor layer is conformally formed on the porous semiconductor layer. The epitaxial semiconductor layer is released from the semiconductor template. Through-holes are selectively formed in the epitaxial semiconductor layer with openings between the front and back lateral surface planes of the epitaxial semiconductor layer to form a partially transparent three-dimensional thin-film semiconductor substrate.

Abstract: The present disclosure presents a three-dimensional thin film solar cell (3-D TFSC) substrate having enhanced mechanical strength, light trapping, and metal modulation coverage properties. The substrate includes a plurality of unit cells, which may or may not be different. Unit cells are defined as a small self-contained geometrical pattern which may be repeated. Each unit cell structure includes a wall enclosing a trench. Further, the unit cell includes an aperture having an aperture diameter. For the purposes of the present disclosure, the dimensions of interest include wall thickness, wall height, and aperture diameter. A pre-determined variation in these dimensions among unit cells across the substrate produces specific advantages.

Abstract: The present disclosure relates to methods for selectively etching a porous semiconductor layer to separate a thin-film semiconductor substrate (TFSS) having planar or three-dimensional features from a corresponding semiconductor template. The method involves forming a conformal sacrificial porous semiconductor layer on a template. Next, a conformal thin film silicon substrate is formed on top of the porous silicon layer. The middle porous silicon layer is then selectively etched to separate the TFSS and semiconductor template. The disclosed advanced etching chemistries and etching methods achieve selective etching with minimal damage to the TFSS and template.

Abstract: A method is presented for fabrication of a three-dimensional thin-film solar cell semiconductor substrate from a template. A semiconductor template having three-dimensional surface features comprising a top surfaces substantially aligned along a (100) crystallographic plane of semiconductor template and a plurality of inverted pyramidal cavities defined by sidewalls substantially aligned along a (111) crystallographic plane is formed according to an anisotropic etching process. A dose of relatively of high energy light-mass species is implanted in the template at a uniform depth and parallel to the top surfaces and said sidewalls defining the inverted pyramidal cavities of the template. The semiconductor template is annealed to convert the dose of relatively of high energy light-mass species to a mechanically-weak-thin layer. The semiconductor template is cleaved along the mechanically-weak-thin layer to release a three-dimensional thin-film semiconductor substrate from the semiconductor template.

Abstract: A method is provided for fabricating a thin-film semiconductor substrate by forming a porous semiconductor layer conformally on a reusable semiconductor template and then forming a thin-film semiconductor substrate conformally on the porous semiconductor layer. An inner trench having a depth less than the thickness of the thin-film semiconductor substrate is formed on the thin-film semiconductor substrate. An outer trench providing access to the porous semiconductor layer is formed on the thin-film semiconductor substrate and is positioned between the inner trench and the edge of the thin-film semiconductor substrate. The thin-film semiconductor substrate is then released from the reusable semiconductor template.

Abstract: A three-dimensional solar cell comprising a semiconductor substrate with an inverted pyramidal cavity, emitter metallization regions on ridges on the surface of the semiconductor substrate which define an opening of the inverted pyramidal cavity, and base metallization regions on a region which form the apex of the inverted pyramidal cavity. A method for fabricating a three-dimensional thin-film solar cell from an inverted pyramidal three-dimensional thin-film silicon substrate by doping ridges on the surface of the semiconductor substrate which define an opening of an inverted pyramidal cavity on the substrate to form an emitter region, and doping a region which forms the apex of the inverted pyramidal cavity to form a base region. Adding a surface passivation layer to the surface of the substrate. Selectively etching the passivation layer from the emitter region and base region. Then concurrently metallizing the emitter region and base region.

Abstract: The present disclosure relates to methods and apparatuses for fracturing or breaking a buried porous semiconductor layer to separate a 3-D thin-film semiconductor semiconductor (TFSS) substrate from a 3-D crystalline semiconductor template. The method involves forming a sacrificial porous semiconductor layer on the 3-D features of the template. A variety of techniques may be used to fracture and release the mechanically weak porous semiconductor layer without damaging the TFSS substrate layer or the template layer such as pressure variations, thermal stress generation, and mechanical bending. The methods also allow for processing three dimensional features not possible with current separation processes. Optional cleaning and final lift-off steps may be performed as part of the release step or after the release step.

Abstract: A three-dimensional thin-film semiconductor substrate having a plurality of ridges on the surface of the semiconductor substrate which define a base opening of an inverted pyramidal cavity and walls defining the inverted pyramidal cavity is provided. And a fabrication method for a 3-D TFSS by forming a porous silicon layer on a silicon template having a top surface aligned along a (100) crystallographic orientation plane of the silicon template and a plurality of walls each aligned along a (111) crystallographic orientation plane of the silicon template and forming an inverted pyramidal cavity. The porous silicon layer forms substantially conformal on the silicon template. Then forming a substantially conformal epitaxial silicon layer on the porous silicon layer and releasing the epitaxial silicon layer from the silicon template.

Abstract: A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.

Abstract: The present disclosure presents a partially-transparent (see-through) three-dimensional thin film solar cell (3-D TFSC) substrate. The substrate includes a plurality of unit cells. Each unit cell structure has the shape of a truncated pyramid, and its parameters may be varied to allow a desired portion of sunlight to pass through.

Abstract: A MEMS device with an overhanging ‘polymer’ capillary provides vital and significant improvements in interfacing a MEMS electrospray nozzle to an MS inlet or other macroscopic instrumentation. The fabrication methodology associated therewith is easily expanded to include built-in micro particle filters and centimeter long serpentine micro channels provided on-chip and fabricated using a low temperature process.

Abstract: The present disclosure relates to methods and apparatuses for fracturing or breaking a buried porous semiconductor layer to separate a 3-D thin-film semiconductor semiconductor (TFSS) substrate from a 3-D crystalline semiconductor template. The method involves forming a sacrificial porous semiconductor layer on the 3-D features of the template. A variety of techniques may be used to fracture and release the mechanically weak porous semiconductor layer without damaging the TFSS substrate layer or the template layer such as pressure variations, thermal stress generation, and mechanical bending. The methods also allow for processing three dimensional features not possible with current separation processes. Optional cleaning and final lift-off steps may be performed as part of the release step or after the release step.

Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.

Abstract: A MEMS device with an overhanging ‘polymer’ capillary provides vital and significant improvements in interfacing a MEMS electrospray nozzle to an MS inlet or other macroscopic instrumentation. The fabrication methodology associated therewith is easily expanded to include built-in micro particle filters and centimeter long serpentine micro channels provided on-chip and fabricated using a low temperature process.

Abstract: A MEMS device with an overhanging ‘polymer’ capillary provides vital and significant improvements in interfacing a MEMS electrospray nozzle to an MS inlet or other macroscopic instrumentation. The fabrication methodology associated therewith is easily expanded to include built-in micro particle filters and centimeter long serpentine micro channels provided on-chip and fabricated using a low temperature process.

Abstract: A MEMS device with an overhanging ‘polymer’ capillary provides vital and significant improvements in interfacing a MEMS electrospray nozzle to an MS inlet or other macroscopic instrumentation. The fabrication methodology associated therewith is easily expanded to include built-in micro particle filters and centimeter long serpentine micro channels provided on-chip and fabricated using a low temperature process.

Abstract: The present disclosure describes a Parylene micro check valve including a micromachined silicon valve seat with a roughened top surface to which a membrane cap is anchored by twist-up tethers. The micro check valve is found to exhibit low cracking pressure, high reverse pressure, low reverse flow leakage, and negligible membrane-induced flow resistance when used as a valve over a micro orifice through which flow liquid and gas fluids.

Abstract: A micromachined fluid handling device having improved properties. The valve is made of reinforced parylene. A heater heats a fluid to expand the fluid. The heater is formed on unsupported silicon nitride to reduce the power. The device can be used to form a valve or a pump. Another embodiment forms a composite silicone/parylene membrane. Another feature uses a valve seat that has concentric grooves for better sealing operation.