Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in memory holes. The memory holes are arranged in rows comprising strings which are grouped into blocks comprising a first plane and a second plane. A control means is configured to program memory cells of the first plane and the second plane connected to one of the word lines using iterations of a program operation. The control means terminates programming of the first plane prior to completing programming of the first plane in response to determining the first plane programs slower than the second plane by a predetermined number of the iterations of the program operation. The control means adjusts the predetermined number of the iterations based on an additional verify iteration performed on at least some of the memory cells beyond the iterations of the program operation.

Abstract: A memory apparatus is provided and includes memory cells connected to word lines and coupled to bit lines and configured to retain a threshold voltage corresponding to data states. A control means determines ones of the data states for a first set of the memory cells connected to a selected word line and for a second set of the memory cells connected to at least one neighboring word line. The control means determines which of a plurality of state groups the memory cells of the first and second sets belong according to the data states determined. The control means determines which one of a plurality of bit line voltage biases to be applied to the bit lines coupled to the memory cells of the first set during a verify operation based on a comparison of state groups of the memory cells of the first set and the second set.

Abstract: A non-volatile memory is configured to perform multiple leak tests integrated into a pre-erase process for a set (e.g., block) of non-volatile memory cells after the set of non-volatile memory cells have received programming. An inference circuit is configured to use results of the leak tests with a pre-trained model to predict whether the set of non-volatile memory cells will fail.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory device also includes control circuitry that is configured to perform a programming operation or an erasing operation. During the programming or erasing operation, the circuitry is configured to, while applying a voltage to at least one selected word line of the plurality of word lines, measure a word line resistance/capacitance (WLRC). The circuitry is also configured to, in response to the WLRC being inside of a predetermined range, continue the programming or erasing operation. The circuitry is further configured to, in response to the WLRC being outside of the predetermined range, establish that the memory block has a short and quarantine the memory block.

Abstract: A memory apparatus includes memory cells each connected to word lines. The memory cells store a threshold voltage and are disposed in memory holes each defining a channel. The memory holes are grouped into a plurality of strings. A control means is configured to apply at least one erase pulse to the channel of the memory holes of all of the plurality of strings. The control means applies an erase verify voltage to the word lines and successively determine whether at least some of the memory cells of ones of the plurality of strings being erased have the threshold voltage below the erase verify voltage in a plurality of subsequent erase verify iterations. The application of the erase verify voltage to the word lines is maintained constantly throughout an entire duration of the plurality of subsequent erase verify iterations for the at least some of the memory cells.

Abstract: In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.

Abstract: A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.

Abstract: In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.

Abstract: Technology for managing non-volatile memory. A bitmap may be maintained in NAND memory cells. The bits in the bitmap map to an address (e.g., PBA) in the NAND memory cells. Each bit has either a first value to indicate that the corresponding address stores valid data or a second value to indicate that the corresponding address does not store value data. Garbage collection may be performed based on the bitmap. Bit-level memory operations are performed to maintain the bitmap. Bit-level erase may be performed to erase a memory cell to have a value that indicates a valid/invalid status. The bitmap may contain unencoded data. In one aspect, a one's complement to the bitmap is stored in the NAND memory cells. The one's complement has opposite values as the regular bitmap. The system may compare the values in the regular bitmap and the one's complement bitmap for data integrity.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage. A control means is coupled to the plurality of word lines and is configured to apply at least one programming pulse of a program voltage to selected ones of the plurality of word lines during at least one programming loop of a programming operation. The control means is also configured to reduce the threshold voltage of the memory cells targeted for an erased state during a bit-level erase operation following the programming operation.

Abstract: In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in memory holes. The memory holes are arranged in rows comprising strings which are grouped into blocks comprising a first plane and a second plane. A control means is configured to program memory cells of the first plane and the second plane connected to one of the word lines using iterations of a program operation. The control means terminates programming of the first plane prior to completing programming of the first plane in response to determining the first plane programs slower than the second plane by a predetermined number of the iterations of the program operation. The control means adjusts the predetermined number of the iterations based on an additional verify iteration performed on at least some of the memory cells beyond the iterations of the program operation.

Abstract: A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.

Abstract: A flash memory includes an improved error handling algorithm for data recovery. Rather than running a default read recovery only, an Enhance Read Retry (ERR) process also is performed. After running a default read recovery, WLs are flagged with an error flag if the read was unsuccessful. The flag triggers ERR mode. ERR mode implements increase of the row read bias or implements increase of row read time or implements multiple pulses at the same voltage, or a combination of all three.

Abstract: Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.

Abstract: Technology is disclosed herein compensating for neighbor memory cell interference on a target memory cell when reading the target memory cell. The voltage that is applied to the bit line associated with the target memory cell may have a magnitude that depends on the data state of the neighbor memory cell. The magnitude of the voltage on the bit line may impact the amount of drain-induced barrier lowering (DIBL) experienced by the target memory cell. The amount of DIBL may be used to provide a desired amount of compensation for the neighbor memory cell interference. A higher bit line voltage may be used to create a greater amount of DIBL and therefore greater amount of compensation for neighbor memory cell interference.

Abstract: The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

Abstract: A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.

Abstract: The memory device includes a plurality of memory cell that arranged in an array, which includes a plurality of channels that are in electrical communication with a source line. The memory device also includes a controller that is configured to erase the memory cells in at least one erase pulse. During the at least one erase pulse, the controller is configured to drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick. The controller is then configured to reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse, including after the voltage of the source line has been reduced to the erase voltage Vera.

Abstract: In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.