Abstract: A processing unit comprising: a processor; and a memory, coupled to the processor and adapted to provide a plurality of enclaves isolated from each other, where the plurality of enclaves include a plurality of application enclaves, each of the application enclaves is used for running a respective application program, and the plurality of enclaves further include at least one of the following: a runtime enclave adapted to provide a storage space required for an invokable program; and a crypto enclave adapted to provide a storage space required for a crypto related program, wherein the runtime enclave and the crypto enclave have read/write permission for the plurality of application enclaves, and each of the application enclaves has no read/write permission for the runtime enclave and the crypto enclave.

Abstract: A processing apparatus, an embedded system, a system-on-chip, and a security control method are disclosed. The processing apparatus includes a processor, adapted to execute a program; and a memory, coupled to the processor and adapted to provide a plurality of enclaves isolated from each other. One of the plurality of enclaves is a source enclave, another one of the plurality of enclaves is a target enclave, and the source enclave and the target enclave each are used to provide a storage space required for running a corresponding program. The processing apparatus further comprises a storage access controller, adapted to transmit specified data stored in the source enclave to the target enclave.

Abstract: A multiplication unit includes first, second, third and fourth receiving terminals, arithmetic units and multiplexers. In complex number mode, the first and second receiving terminals receive a real part value and an imaginary part value of a first complex number, respectively, whereas the third and fourth receiving terminals receive a real part value and an imaginary part value of a second complex number, respectively. In modulus mode, the first and third receiving terminals receive first and second integers, respectively. The multiplexers gate the arithmetic units to perform a complex number multiplication operation according to the first and second complex numbers to generate a third complex number in complex number mode and perform a modulus multiplication operation according to the first and second integers and a predetermined modulus to generate a third integer in modulus mode.

Abstract: The present disclosure discloses a processor and a multi-core processor. The processor includes a processor core and a memory. The processor core includes a homomorphic encryption instruction execution module and a general-purpose instruction execution module; the homomorphic encryption instruction execution module is configured to perform homomorphic encryption operation and includes a plurality of instruction set architecture extension components, wherein the plurality of instruction set architecture extension components are respectively configured to perform a sub-operation related to the homomorphic encryption; the general-purpose instruction execution module is configured to perform non-homomorphic encryption operation. The memory is vertically stacked with the processor core and is used as a cache or scratchpad memory of the processor core.

Abstract: The present application discloses a computing accelerator, a data processor and an associated method for homomorphic encryption. The computing accelerator is configured to perform computations on input polynomials to generate output polynomials. The input polynomials are ciphertexts generated from a plaintext data after ring learning with error encryption, and the output polynomials correspond to a result after performing a linear computation on the plaintext data. The computing accelerator includes a polynomial multiplying unit, a coefficient extraction unit, and ciphertext wrapping unit. The polynomial multiplication unit multiplies a first input polynomial with a second input polynomial to generate an intermediate polynomial. The coefficient extraction unit converts the intermediate polynomial into a target polynomial according to a target coefficient in the intermediate polynomial. The ciphertext wrapping unit generates an output polynomial according to at least the target polynomial.

Abstract: The present application discloses a calculator and a method thereof. The calculator is configured to accelerate the number-theoretic transformation of a 2N-dimensional polynomial. The calculator includes a first coefficient memory, a second coefficient memory, a twiddle factor memory, a plurality of processing units and a data flow controller. In the odd-number rounds of coefficient computation operations, the processing units perform first calculation procedures to read coefficients from the first coefficient memory for modulo calculation, and perform first writing procedures to write output coefficients to the second coefficient memory. In even-number rounds of coefficient computation operations, the processing units performs second calculation procedures to read coefficients from the second coefficient memory for modulo calculations, and perform second writing procedures to write output coefficients to the first coefficient memory.

Abstract: The present disclosure provides an acceleration unit, and a related apparatus and method. The acceleration unit includes: one or more number theoretic transform units adapted to perform number theoretic transform during homomorphic encryption; one or more arithmetic logic units adapted to perform an arithmetic operation during homomorphic encryption; and a scheduler adapted to assign an operation in a to-be-executed homomorphic encryption instruction to at least one of the one or more number theoretic transform units and at least one of the one or more arithmetic logic units. Embodiments of the present disclosure improve versatility, global performance, and scalability of deployment of homomorphic encryption hardware.

Abstract: A processing apparatus, an embedded system, a system-on-chip, and a security control method are disclosed. The processing apparatus includes a processor, adapted to execute a program; and a memory, coupled to the processor and adapted to provide a plurality of enclaves isolated from each other. One of the plurality of enclaves is a source enclave, another one of the plurality of enclaves is a target enclave, and the source enclave and the target enclave each are used to provide a storage space required for running a corresponding program. The processing apparatus further comprises a storage access controller, adapted to transmit specified data stored in the source enclave to the target enclave.

Abstract: A processing unit comprising: a processor; and a memory, coupled to the processor and adapted to provide a plurality of enclaves isolated from each other, where the plurality of enclaves include a plurality of application enclaves, each of the application enclaves is used for running a respective application program, and the plurality of enclaves further include at least one of the following: a runtime enclave adapted to provide a storage space required for an invokable program; and a crypto enclave adapted to provide a storage space required for a crypto related program, wherein the runtime enclave and the crypto enclave have read/write permission for the plurality of application enclaves, and each of the application enclaves has no read/write permission for the runtime enclave and the crypto enclave.