Abstract: A processing device includes: a receiving module for receiving a configuration from a control device, wherein the configuration includes a destination address, a length, a filled value and a function type; a control module for (A) configuring an access state for accessing a slave device according to the function type and (B) comparing a counting value with the length to generate a comparison result according to the function type, determining whether data received from the slave device reaches an end to generate a determination result, or both; a reading module for reading the data according to the access state; a writing module for writing the filled value to the destination address according to information of the access state, the determination result and the comparison result; and a transmitting module for transmitting an interrupt signal to the control device according to result(s) of the determination result and the comparison result.

Abstract: A data storage system includes a first memory, a second memory, and a memory controller. The memory controller transmits a first data segment from the first memory to the second memory according to an initial address, adds a first interval value to the initial address to generate a succeeding address, and updates a stream number. When the stream number has not reached a target stream number, the memory controller transmits second data segment from the first memory to the second memory according to the succeeding address, and updates the stream number. When the stream number has reached the target stream number, the memory controller sets the stream number to an initial value, adds an offset value to the initial address to update the succeeding address, and transmits a third data segment from the first memory to the second memory according to the updated succeeding address.

Abstract: A data storage system includes a first memory, a second memory, and a memory controller. The memory controller transmits a first data segment from the first memory to the second memory according to an initial address, adds a first interval value to the initial address to generate a succeeding address, and updates a stream number. When the stream number has not reached a target stream number, the memory controller transmits second data segment from the first memory to the second memory according to the succeeding address, and updates the stream number. When the stream number has reached the target stream number, the memory controller sets the stream number to an initial value, adds an offset value to the initial address to update the succeeding address, and transmits a third data segment from the first memory to the second memory according to the updated succeeding address.