Patents by Inventor Xubin Tan

Xubin Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of managing task dependencies at runtime in a parallel computing system of a hardware processing system and a hardware acceleration processor
    Patent number: 11436048
    Abstract: Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: September 6, 2022
    Assignees: Barcelona Supercomputing Center—Centro Nacional De Supercomputacion, Universitat Politecnica De Catalunya
    Inventors: Xubin Tan, Carlos Alvarez Martinez, Jaume Bosch Pons, Daniel Jimenez Gonzalez, Mateo Valero Cortes
  • Managing Task Dependency
    Publication number: 20200110634
    Abstract: Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.
    Type: Application
    Filed: July 24, 2017
    Publication date: April 9, 2020
    Applicants: Barcelona Supercomputing Center - Centro Nacional De Supercomputacion, Universitat Politecnica De Catalunya
    Inventors: Carlos Alvarez Martinez, Jaume Bosch Pons, Daniel Jimenez Gonzalez, Xubin Tan, Mateo Valero Cortes