Abstract: The present disclosure relates to the technical field of campus local area networks (LANs), and particularly discloses a method and system for implementing multi-service bearer in a passive optical LAN (POL). The method includes: step S1: constructing a POL, and accessing an entire campus network at a bandwidth of Gigabit according to a point-to-multipoint star topology including three layers: a core layer, a convergence layer, and an access layer, to form a 10 Gbit backbone, wherein an optical network terminal enters a room and is deployed according to such a manner that one classroom or functional room has one terminal mode; step S2: planning and managing the entire POL, defining a plurality of LANs through software definition (SD-LAN), wherein different LANs bear different services; and step S3: allocating different service bandwidths to different LANs through a sharding mechanism of the PON, and the like.

Abstract: Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.

Abstract: Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.