Abstract: Soft sensing of nonlinear and multimode industrial processes given a limited number of labeled data samples is disclosed. Methods include a semi-supervised probabilistic density-based regression approach, called Semi-supervised Weighted Gaussian Regression (SWGR). In SWGR, different weights are assigned to each training sample based on their similarities to a query sample. Then a local weighted Gaussian density is built for capturing the joint probability of historical samples around the query sample. The training process of parameters in SWGR incorporates both labeled and unlabeled data samples via a maximum likelihood estimation algorithm. In this way, the soft sensor model is able to approximate the nonlinear mechanics of input and output variables and remedy the insufficiency of labeled samples. At last, the output prediction as well as the uncertainty of prediction can be obtained by the conditional distribution.

Abstract: The present technology provide compositions that are drug delivery systems for the sustained release of anti-stenotic drugs for the treatment and prevention of occlusion of blood vessels, particularly after perivascular surgery. The compositions include a hydrogel, unimolecular micelles dispersed within the hydrogel, and an effective amount of anti-stenotic drug dispersed within the unimolecular micelle. The hydrogel may be a di-or tri-block copolymer comprising one block of poly(ethylene glycol) (PEG) and one or two blocks of poly(lactic-co-glycolic acid) (PLGA). The unimolecular micelle may include three domains: a dendritic polymer core, hydrophobic block polymers (e.g., PVL, PVCL, and/or PCL) attached to the core and PEG attached to the hydrophobic block polymers.

Abstract: An apparatus includes an interface and a training circuit. The interface may be configured to transmit signals to/from a plurality of I/O channels. The training circuit may be configured to generate a training voltage on a current one of the I/O channels, read an output of an eye monitor slicer to determine voltage transition values corresponding to the training voltage at a plurality of sampling times, map the voltage transition values to coefficients for the current I/O channel and determine the coefficients for each of the I/O channels. The training circuit may comprise the eye monitor slicer. The voltage transition values may correspond to an interference response for one of the I/O channels. The coefficients may be applied as feedback to cancel the interference.

Abstract: An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop may be configured to determine the control value that results in a given delay between the system clock and the second clock. The second phase interpolator circuit may be in a normal signal path and configured to generate a third clock with the given delay relative to the first clock using the control value such that the third clock is offset from the system clock by the given delay.

Abstract: An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.

Abstract: An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop may be configured to determine the control value that results in a given delay between the system clock and the second clock. The second phase interpolator circuit may be in a normal signal path and configured to generate a third clock with the given delay relative to the first clock using the control value such that the third clock is offset from the system clock by the given delay.

Abstract: An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.

Abstract: An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.

Abstract: A double sliding-plug door system includes a fixed frame, a sliding-plug rail arranged in the fixed frame, a cross beam, a driving mechanism, a linkage mechanism, a guide locking piece and a limiting mechanism. The driving mechanism has a screw rod and a motor driven nut assembly having a transmission frame, a nut sleeved in the screw rod and a follow-up member fixed in the nut; the nut mounted in the transmission frame, which itself is connected with an active sleeve assembly; the screw rod drives the nut assembly to reciprocate axially along the screw rod.

Abstract: An apparatus comprising an input interface an output interface and a coupling interface. The input interface may comprise a plurality of input stages each configured to (i) receive a data signal and a coupled clock signal and (ii) present an intermediate signal. The output interface may comprise a plurality of output stages each configured to (i) receive the intermediate signal from one of the input stages, (ii) receive the coupled clock signal and (iii) present an output signal. The coupling interface may be configured to (i) receive the clock signal and (ii) present the coupled clock signal to each of (a) the input stages and (b) the output stages. The coupling interface may generate a plurality of inductive couples and (b) the inductive couples may enable a synchronization of the coupled clock signal with the clock signal for each of the input stages and the output stages.

Abstract: An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.

Abstract: An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.

Abstract: The present technology provide compositions that are drug delivery systems for the sustained release of anti-stenotic drugs for the treatment and prevention of occlusion of blood vessels, particularly after perivascular surgery. The compositions include a hydrogel, unimolecular micelles dispersed within the hydrogel, and an effective amount of anti-stenotic drug dispersed within the unimolecular micelle. The hydrogel may be a di-or tri-block copolymer comprising one block of poly(ethylene glycol) (PEG) and one or two blocks of poly(lactic-co-glycolic acid) (PLGA). The unimolecular micelle may include three domains: a dendritic polymer core, hydrophobic block polymers (e.g., PVL, PVCL, and/or PCL) attached to the core and PEG attached to the hydrophobic block polymers.

Abstract: The common-mode input voltage of a common-gate input amplifier receiving a differential signal is set in an open-loop manner by basing the bias current and/or source load impedances of the common-gate amplifier on a transmitter bias current and driving impedance. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a closed-loop manner using a feedback loop having a captured target voltage compared to the common-mode input voltage at a node of the amplifier. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a continuous time closed loop manner by sending a reference current through resistances that are multiples of a resistance used to generate the reference current.

Abstract: A method of equalizing an input data signal using a multiple-stage continuous-time linear equalization (CTLE) circuit. A zero-forcing least-mean-square (ZF LMS) procedure is applied to adapt the settings of the CTLE stages. The amplitude settings and the frequency boost settings of the CTLE stages are adapted within the ZF LMS procedure. In an exemplary implementation, an error screening threshold may be applied to an error signal within the ZF LMS procedure to generate a reduced error signal such that weight updates do not occur if the error signal is below the error screening threshold. In addition, if an accumulated sign error signal within the ZF LMS procedure reaches a predetermined maximum indicative of a high loss channel, then a setting for a variable gain amplifier may be increased, and an amplitude setting for the CTLE circuit may be decreased. Other embodiments, aspects and features are also disclosed.

Abstract: Systems and methods are discussed relating to allocation of memory from a fixed pool of fast memory within a data center having a data storage area equipped with that memory. Techniques include: receiving a request to write data in the storage area; identifying a file group associated with the write request; analyzing previous data activity traces associated with the file group; determining an available fast memory amount based on the total amount of fast memory in the fixed pool and a currently allocated amount of fast memory; determining a fast memory allocation for the file group based on the previous data activity traces, the available fast memory, and a fast memory constraint, the memory allocation including an allocation amount and a write probability; and providing information about the memory allocation to a file system of the data center, which writes the data based on the allocation amount and write probability.

Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Abstract: A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the voltage regulator. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the interconnect. In an embodiment of the present invention, a voltage regulator includes an AMP having a bias-generating device, such as a p-type transistor, acting as a current source, having a source coupled to Vdd and a drain coupled to the interconnect. The gate of the bias-generating device is coupled to the gate of four other p-type devices. Each of the four p-type devices has a source coupled to Vdd. The drains of the first and second p-type transistors are coupled to an output providing Ild.

Abstract: A circuit includes a phase interpolator and a self test circuit. The phase interpolator is to provide a interpolator output having a phase corresponding to a respective phase step in a plurality of phase steps. The interpolator output is a weighted combination of one or more of a plurality of phasor signals. The self test circuit includes a phase detector coupled to a reference signal and the interpolator output, a phase-difference-to-voltage converter coupled to the phase detector, an analog-to-digital converter (ADC) coupled to the phase-difference-to-voltage converter, and control logic. The phase detector is to generate an output that is proportional to a phase difference between the reference signal and the interpolator output. The phase-difference-to-voltage converter is to convert the output from the phase detector into a corresponding voltage. The ADC is to convert an output from the phase-difference-to-voltage converter into a corresponding digital value.

Abstract: A circuit includes a phase interpolator and a self test circuit. The phase interpolator is to provide a interpolator output having a phase corresponding to a respective phase step in a plurality of phase steps. The interpolator output is a weighted combination of one or more of a plurality of phasor signals. The self test circuit includes a phase detector coupled to a reference signal and the interpolator output, a phase-difference-to-voltage converter coupled to the phase detector, an analog-to-digital converter (ADC) coupled to the phase-difference-to-voltage converter, and control logic. The phase detector is to generate an output that is proportional to a phase difference between the reference signal and the interpolator output. The phase-difference-to-voltage converter is to convert the output from the phase detector into a corresponding voltage. The ADC is to convert an output from the phase-difference-to-voltage converter into a corresponding digital value.