Abstract: A technique includes providing a butter to receive data from a processor of a wireless device in response to an active mode of the processor and selectively coupling an input terminal of a filter to the buffer based on a status of the buffer. The techniciue may be used with a wireless system that includes a digital signal processor, a buffer, a wireless interface and a switch. The buffer receives data from the digital signal processor in response to an active mode of the digital signal processor. The switch selectively couples a terminal of the wireless interface to the buffer in response to a determination of a status of the buffer.

Abstract: A technique that includes providing a buffer to receive data from a processor of a wireless device in response to an active mode of the processor and selectively coupling an input terminal of a filter to the buffer based on a status of the buffer.

Abstract: In one embodiment, the present invention includes methods and apparatus for providing initial control values to programmable load capacitors of an oscillator, such as that of a real time clock circuit. Using the initial values, the real time clock circuit may begin operation, enabling additional circuitry within an integrated circuit to begin operation. This additional circuitry may cause operating values to program the load capacitors to provide a desired reference clock based on a given system's requirements.

Abstract: In one embodiment, a power supply switching circuit may automatically provide power to a clock circuit from one of an auxiliary power supply and a main power supply, based on a voltage of the main power supply. To provide automatic switching, a switch circuit coupled between the power supplies and the clock circuit may be controlled by a voltage detector, in some embodiments.

Abstract: A wireless communication system is provided that includes RF circuitry and signal processing circuitry. The signal processing circuitry includes a dedicated frequency burst (FB) search hardware circuit which exhibits relatively low noise in comparison with other digital processing circuitry, such as a DSP and MCU, within the system. The RF circuitry, dedicated FB search hardware circuit and the other digital processing circuitry can each be activated and inactivated. In one embodiment, when the RF circuitry and the dedicated FB search hardware are active, other digital processing circuitry remains inactive to avoid noise problems that could degrade reception and interfere with the FB search hardware locating the FB. Noise problems in the system are thus desirably reduced.

Abstract: In one aspect, the present invention is a technique of, and a system and sensor for measuring, inspecting, characterizing and/or evaluating the performance of high-speed data communication systems, and components used therein. In one embodiment, the present invention measures, inspects, characterizes and/or evaluates the performance, for example the ER, of such systems and/or components in situ—that is, in the environment and/or in the configuration in which the system and/or components are used during normal or typical operation (for example, when the system and/or component is transmitting and receiving user data). In this way, a more accurate representation of the performance of the system (and components thereof) may be measured, detected, determined and/or obtained.

Abstract: In one aspect, the present invention is a technique of, and a system and sensor for measuring, inspecting, characterizing and/or evaluating the performance of high-speed data communication systems, and components used therein. In one embodiment, the present invention measures, inspects, characterizes and/or evaluates the performance, for example the ER, of such systems and/or components in situ—that is, in the environment and/or in the configuration in which the system and/or components are used during normal or typical operation (for example, when the system and/or component is transmitting and receiving user data). In this way, a more accurate representation of the performance of the system (and components thereof) may be measured, detected, determined and/or obtained.

Abstract: In one aspect, the present invention is a technique of, and a system and sensor for measuring, inspecting, characterizing and/or evaluating the performance of high-speed data communication systems, and components used therein. In one embodiment, the present invention measures, inspects, characterizes and/or evaluates the performance, for example the ER, of such systems and/or components in situ—that is, in the environment and/or in the configuration in which the system and/or components are used during normal or typical operation (for example, when the system and/or component is transmitting and receiving user data). In this way, a more accurate representation of the performance of the system (and components thereof) may be measured, detected, determined and/or obtained.

Abstract: A gain ranging AD converter is provided having two separate gain paths. There is provided a low-gain path and a high-gain path. The low gain path is processed through an analog modulator (333) and then through a filter section to provide on an output of a high-pass filter (339), a low-gain signal which is then compensated for in an equalizer section (347). This equalizing section (347) calibrates the output signal to ensure that the difference between the calibrated signal and the high-gain signal differs only by the fixed gain between the two paths. The high-gain path also includes a modulator (335) for processing through a filter section to provide on the output of a high-pass filter section (343) a high-gain signal. A calibration generator (361) is utilized to generate the parameters for performing the equalization.

Abstract: A multi-bit DAC (109) is provided as part of a digital-to-analog data converter (DAC). The multi-bit DAC is comprised of a plurality of single-bit DACs (503) which have the values thereof selected through a digital encoder (505). The digital encoder (505) performs dynamic element matching (DEM) on an input data value. The sequence of selection is performed such that the element mismatch noise response of the DAC (109) is shaped. The outputs are summed at a summing junction (507) and then filtered with a low pass filter (113). In the noise shaping response, a cyclical second order response is provided with a Data Weighted Averaging (DWA) technique wherein the outputs of the DACs are restricted to one of two states. To achieve this, select ones of the output values are changed in order to comply with this restriction, thus deviating from a uniform element selection algorithm. This provides a constrained second order response which accounts for mismatching of the DAC elements (503).

Abstract: An analog-to-digital converter is provided for producing digital signal representative of analog signals. Noise induced upon the digital signals can be substantially removed using a digital decimation filter. The decimation filter includes a front-end portion which receives the digital data at a relatively high sample rate and performs filtering operations with minimal complexity. Preferably, the front-end portion includes at least one stage of filtering and more preferably at least two filter stages, each of which perform interpolation separate from decimation. According to one embodiment, the first stage of the front-end portion involves decimation and the latter stage or stages of that portion involves a combination of interpolation and decimation. The cumulative effect is to reduce the sample rate of the incoming data stream produced by, for example, a quantizer to a value which can be more easily manipulated by the back-end portion of the digital decimation filter.

Abstract: Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.

Abstract: A delta-sigma analog/digital converter is provided for operating in the analog domain to generate a digital value that is to be processed by a digital signal processor (DSP) (26) to provide on the output a digital output. Each data node in each processing element in the DSP (26) is mirrored by the way of a corresponding data node in the mirror circuit (36). This results in the addition of noise via a noise adder (28) such that each data node in the main portion of the DSP (26) that can draw current from the power supply during a transition will have a corresponding complement node in the mirror circuit (36). Each data node in the mirror circuit will add noise via a transition drawing current from the power supply whenever the transition does not occur at the corresponding data node in the main portion of the DSP (26). Therefore, di/dt noise will be added for each cycle, regardless of the data pattern.

Abstract: A delta-sigma analog/digital converter is provided for operating in the analog domain to generate a digital value that is to be processed by a digital signal processor (DSP) (26) to provide on the output a digital output. Each data node in each processing element in the DSP (26) is mirrored by the way of a corresponding data node in the mirror circuit (36). This results in the addition of noise via a noise adder (28) such that each data node in the main portion of the DSP (26) that can draw current from the power supply during a transition will have a corresponding complement node in the mirror circuit (36). Each data node in the mirror circuit will add noise via a transition drawing current from the power supply whenever the transition does not occur at the corresponding data node in the main portion of the DSP (26). Therefore, di/dt noise will be added for each cycle, regardless of the data pattern.