Abstract: A non-volatile semiconductor memory device comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.

Abstract: A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a source line connected to a set of the non-volatile storage elements. The one or more control circuits are further configured to perform the program iteration of the program operation on the set of non-volatile storage elements, where the program iteration includes applying the set of voltage levels to the source line.

Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line, during the second pass, a voltage that is applied to at least one memory cell is reduced from a verify voltage by an offset which is determined as a function of a data state of an adjacent memory cell of an adjacent word line and wherein the first pass but not the second pass has been completed in the adjacent word line.

Abstract: Apparatuses and techniques are described for reducing the program time for a set of memory cells by using an enhanced step up of a program bias. A program operation includes a first pass in which memory cells are programmed to intermediate states and a second program pass in which the memory cells are programmed from an erased state and the intermediate states to final states. In the first program pass, program time can be reduced by applying an enhanced program bias step up to memory cells of the highest intermediate state in a single program loop, for example. The enhanced program bias step up can be achieved by applying a negative bit line voltage and can be triggered when the memory cells assigned to the second highest intermediate state reach a program milestone such as completing programming.

Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line, during the second pass, a voltage that is applied to at least one memory cell is reduced from a verify voltage by an offset which is determined as a function of a data state of an adjacent memory cell of an adjacent word line and wherein the first pass but not the second pass has been completed in the adjacent word line.

Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.

Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to receive a parity bit that has been stored using a data structure, and to receive a first subset of host data that includes block data relating to a set of memory cells. The control circuitry may be configured to perform a read operation to identify a second subset of host data that includes additional block data relating to the set of memory cells. The control circuitry may be configured to decode the second subset of host data using the parity bit. The control circuitry may be configured to perform a write operation to write the block data to at least one or more memory cells that are part of the set of memory cells.

Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.