Patents by Inventor Xue Ren

Xue Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240013548
    Abstract: An obstacle recognition method includes the steps of: determining a candidate obstacle region in a candidate weeding region image according to color information of the candidate weeding region image; obtaining contour information of the candidate obstacle region and value information of the candidate weeding region image; and determining, according to the contour information and the value information, whether there is an obstacle in the candidate weeding region image. A related obstacle recognition apparatus, an electronic device, a computer-readable storage medium, and a weeding robot are also disclosed.
    Type: Application
    Filed: November 30, 2020
    Publication date: January 11, 2024
    Inventors: Shaoming Zhu, Xue Ren
  • Publication number: 20230385987
    Abstract: Disclosed are a roughness compensation method and system, an image processing device, and a readable storage medium. The roughness compensation method includes the following steps: acquiring a roughness value of a target region in an image and position information of pixels in the target region; averaging the position information of the pixels in the target region to obtain average position information; determining whether the average position information is located in a preset compensation region; and compensating and updating the roughness value when the average position information is located in the preset compensation region; or skipping compensating the roughness value when the average position information is not located in the preset compensation region.
    Type: Application
    Filed: October 28, 2020
    Publication date: November 30, 2023
    Inventors: Shaoming Zhu, Xue Ren
  • Publication number: 20230368394
    Abstract: An image segmentation method includes the steps of: obtaining a hue histogram corresponding to a hue channel image based on an original image; determining a target parameter value based on the hue histogram; determining a saturation segmentation threshold as a first threshold range if the target parameter value satisfies a preset condition, otherwise determining the saturation segmentation threshold as a second threshold range, where a minimum value of the first threshold range is greater than a minimum value of the second threshold range; and performing image segmentation in combination with the first threshold range or the second threshold range as determined in the previous step. Related apparatus, computer devices, and computer readable storage media are also disclosed.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 16, 2023
    Inventors: Shaoming Zhu, Xue Ren
  • Publication number: 20230351603
    Abstract: The present disclosure relates to an image segmentation method based on a chrominance component. The method includes the following steps: obtaining a chrominance component of an image; generating a chrominance component histogram according to the chrominance component; determining peaks and troughs in the chrominance component histogram according to a preset chrominance interval and preset peak and trough setting conditions; obtaining a segmentation threshold according to the peaks and the troughs; and segmenting the image into a plurality of regions with different chrominances according to the segmentation threshold. In the present disclosure, the segmentation threshold is obtained according to the peaks and the troughs, the segmentation threshold is dynamically adjusted according to different images, and a fixed segmentation threshold is not used, thereby effectively reducing false segmentation.
    Type: Application
    Filed: October 28, 2020
    Publication date: November 2, 2023
    Inventors: Shaoming Zhu, Xue Ren
  • Publication number: 20230315106
    Abstract: The present invention provides an automatic charging method and system for a robot, a robot, and a storage medium. The method comprises: S1, recording coordinates of a position A of a charging station; S2, when the robot receives a charging instruction, recording coordinates of a current position B of the robot; S3, after driving the robot to walk a preset distance straight with the coordinates of the position B as a starting point, recording coordinates of a current position C of the robot; S4, calculating a deflection angle and deflection direction of the robot relative to the charging station according to the coordinates of the position A, the position B and the position C; and S5, driving the robot to search for and arrive at the charging station according to the deflection angle and deflection direction.
    Type: Application
    Filed: November 20, 2020
    Publication date: October 5, 2023
    Inventors: Xue Ren, Shaoming Zhu
  • Patent number: 9704726
    Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 11, 2017
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Chin Hock Toh, Yi Sheng Anthony Sun, Xue Ren Zhang, Ravi Kanth Kolan
  • Publication number: 20160005629
    Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.
    Type: Application
    Filed: September 18, 2015
    Publication date: January 7, 2016
    Inventors: Chin Hock TOH, Yi Sheng Anthony SUN, Xue Ren ZHANG, Ravi Kanth KOLAN
  • Patent number: 9142487
    Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 22, 2015
    Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Chin Hock Toh, Yi Sheng Anthony Sun, Xue Ren Zhang, Ravi Kanth Kolan
  • Patent number: 8647924
    Abstract: A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: February 11, 2014
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Chin Hock Toh, Keng Yuen Au, Reynaldo Vincent Hernandez Sta Agueda, Bee Liang Catherine Ng, Librado Amurao Gatbonton, Xue Ren Zhang, Yi-Sheng Anthony Sun
  • Patent number: 8384203
    Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: February 26, 2013
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Chin Hock Toh, Yi Sheng Anthony Sun, Xue Ren Zhang, Ravi Kanth Kolan
  • Publication number: 20100261313
    Abstract: A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 14, 2010
    Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Chin Hock TOH, Keng Yuen AU, Reynaldo Vincent Hernandez STA AGUEDA, Bee Liang Catherine NG, Librado Amurao GATBONTON, Xue Ren ZHANG, Yi-Sheng Anthony SUN
  • Publication number: 20100109169
    Abstract: A stiffener is provided for use in making semiconductor devices. The stiffener and method of use provided prevent or reduce warpage of a semiconductor package during the assembly process. More particularly, the stiffener functions to prevent or reduce warpage during molding of an assembly of wafers and/or dies. The stiffener may be positioned above the backside or non-active side of an assembly of wafer and/or dies during molding. The presence of the stiffener prevents or reduces warpage caused by CTE mismatch between the mold material and the wafer and/or under the high temperatures encountered in the process of molding. After molding, the stiffener may continue to provide support to the assembly.
    Type: Application
    Filed: April 28, 2009
    Publication date: May 6, 2010
    Applicant: UNITED TEST AND ASSEMBLY CENTER LTD
    Inventors: Ravi Kanth KOLAN, Anthony Yi-Sheng Sun, Chin Hock Toh, Catherine Bee Liang Ng, Xue Ren Zhang
  • Publication number: 20100013081
    Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.
    Type: Application
    Filed: July 20, 2009
    Publication date: January 21, 2010
    Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Chin Hock TOH, Yi Sheng Anthony SUN, Xue Ren ZHANG, Ravi Kanth KOLAN