Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data detection. As one example, a data processing system is described that includes a variance calculation circuit operable to calculate a variance of a data input; and a branch metric calculation circuit operable to calculate a branch metric based at least in part on the variance.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for fragmenting a data set and recovering the fragmented data set. As one example, a data processing system is discussed that includes: a fragmenting circuit operable to separate a data set into at least a first fragment and a second fragment; and a transfer packet formation circuit operable to: append identification information to the front of the first fragment, and at least a first M+N bits of the second fragment to the end of the first fragment to yield a first transfer fragment, and aggregate the first transfer fragment with other transfer fragments to yield an aggregate output.

Abstract: A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.

Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for calibration during data processing. As an example, a data processing system is discussed that includes a sample averaging circuit operable to average digital samples from an analog to digital converter circuit over multiple instances of an analog input to yield an X-average output, and a selector circuit operable to select one of the digital samples or the X-average output as a processing output.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for coasting one or more calibration loops based upon identification of a probability of data inaccuracies. One embodiment is a data processing system that includes: a defect detector circuit operable to identify a defect region during a first pass processing of a received data set; a defect location buffer operable to maintain an indication of the defect region in the received data set; and a calibration circuit operable to adaptively update a calibration output during a second pass processing of the received data set, where updating the calibration output is disabled for one or more samples of the received data set corresponding to the indication of the defect region.

Abstract: A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.

Abstract: A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.

Abstract: A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for fragmenting a data set and recovering the fragmented data set.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set.

Abstract: A data processing system includes a digital data input operable to receive digital data, a digital data values input operable to receive values of the digital data, a loop pulse response estimation circuit operable to calculate a loop pulse response based on the digital data and the values of the digital data and based at least in part on past values of the loop pulse response, and a scaling circuit operable to scale the loop pulse response based at least in part on an absolute sum of the loop pulse response to yield a scaled loop pulse response.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data detection.

Abstract: The present invention is related to systems and methods for enhancing data detection in a data processing system. In one embodiment, a data processing system is disclosed that includes a data detector circuit that is governed at least in part based upon selected coefficients. The selected coefficients are selected as either a first set of coefficients or a second set of coefficients where the second set of coefficients has fewer coefficients than the first set of coefficients.

Abstract: Various embodiments of the present invention provide systems and methods for handling out of order reporting in a storage device.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for bit error rate prediction in a data processing system.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for bit error rate prediction in a data processing system.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. Such systems and methods may include data pre-processing and detection to identify a media defect.

Abstract: Methods and apparatus are provided for detecting a sync mark in a storage system, such as a hard disk drive. A sync mark is detected in a storage system by obtaining one or more branch metrics from a data detector in the storage system; generating one or more sync mark metrics using the one or more branch metrics from the data detector; and identifying the sync mark based on the sync mark metrics. An input data set is optionally compared with a plurality of portions of a sync mark pattern to yield corresponding comparison values and the comparison values can be summed to obtain at least one result. A sync mark found signal is asserted based upon the at least one result.

Abstract: Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset.