Abstract: A start-up circuit in a switch-mode power converter that employs a Zener diode to provide a reference voltage to reduce the power consumption and the size of the start-up circuit. The start-up circuit also includes a coarse current source and a coarse reference voltage signal generator for producing current and reference voltage for initial startup operation of a bandgap circuit. The reference signal and current from coarse current source and the reference voltage signal generator are subject to large process, voltage and temperature (PVT) variations or susceptible to noise from the power supply, and hence, these signals are used temporarily during start-up and replaced with signals from higher performance components. After bandgap circuit becomes operational, the start-up receives voltage reference signal from the bandgap circuit to more accurately detect undervoltage lockout conditions.

Abstract: An adaptive switch mode LED driver provides an intelligent approach to driving multiple strings of LEDs. The LED driver determines an optimal current level for each LED channel from a limited set of allowed currents. The LDO driver then determines a PWM duty cycle for driving the LEDs in each LED channel to provide precise brightness control over the LED channels. Beneficially, the LED driver minimizes the power dissipation in the LDO circuits driving each LED string, while also ensuring that the currents in each LED string are maintained within a limited range. A sample and hold LDO allows PWM control over extreme duty cycles with very fast dynamic response. Furthermore, fault protection circuitry ensures fault-free startup and operation of the LED driver.

Abstract: A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.

Abstract: A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.

Abstract: A digital phase lock loop circuit with reduced jitter at the output is disclosed. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.

Abstract: Methods are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal.

Abstract: A voltage-to-current converter providing an output current with compensation for process-voltage-temperature (PVT) variations of a component in the voltage-to-current converter. The voltage-to-current converter includes a first voltage-to-current converter branch, a second voltage-to-current converter branch, and a compensation current path. The first voltage-to-current converter provides a first current to the output of the voltage-to-current converter based on a variable control voltage. The second voltage-to-current converter branch provides a second current based on a fixed voltage. The compensation current path provides a compensation current from the second voltage-to-current branch to the first voltage-to-current converter branch compensating variations in the first current caused by the PVT variations of the component in the first voltage-to-current converter branch.

Abstract: Methods and devices are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. In one embodiment, a predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal and to thereby provide fairly good guesses.

Abstract: A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.

Abstract: Methods and devices perform analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal to thereby provide fairly good guesses.

Abstract: A reference buffer includes a first current mirror, a second current mirror, a first source follower coupled in series to a branch of the first current mirror and receiving a first initial reference voltage and outputting a first reference voltage, a second source follower coupled in series to a branch of the second current mirror and receiving a second initial reference voltage and outputting a second reference voltage, and a resistor coupled between a first node and a second node outputting the first and second reference voltages, respectively. The first node is disposed between the first current mirror and the first source follower and the second node is disposed between the second current mirror and the second source follower. The voltage difference between the first reference voltage and the first initial reference voltage is substantially same as that between the second reference voltage and the second initial reference voltage.

Abstract: A low dropout (LDO) voltage regulator having more than one LDO modules, each LDO module having a frequency response adapted to a certain range of output frequency. The LDO voltage regulator can provide a gain over a broad range of operating frequency by combining output current from each LDO module and providing the combined current at an output of the LDO voltage regulator. The LDO voltage regulator further comprises a load monitor coupled to the LDO modules for disabling some of the LDO modules to reduce power consumption of the LDO voltage regulator.

Abstract: Methods and devices are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. In one embodiment, a predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal and to thereby provide fairly good guesses.

Abstract: There is described a cMUT array with transducer elements which include a plurality of cells with membranes formed on one surface of a wafer. Voltages applied between said spaced electrodes drive said membranes. The voltages applied to said electrodes are applied from the opposite surface of the wafer through the wafer and through vias formed in the wafer.

Abstract: There is provided an acoustic transducer which includes a membrane of selected size and shape supported at its edges spaced from a first conductive electrode by an integral support structure with the second conductive electrode comprising a thin metal film on the membrane. The active membrane area is undisturbed by etch vias.