Abstract: The present disclosure discloses an array substrate and a detection method therefor, a display panel, and a display device. The array substrate includes: a base substrate, wherein the base substrate has a display area and a peripheral area surrounding the display area; a plurality of sub-pixel units, wherein the plurality of sub-pixel units are arrayed in the display area; a plurality of data lines, wherein the data lines are electrically connected to the sub-pixel units in corresponding columns; at least one first switching transistor, wherein the first switching transistor is located at a first side of the peripheral area, a drain of the first switching transistor is electrically connected to one of the data lines, and the data line connected to the drain of the first switching transistor is a first data line; a gate control line; and at least one detection line.

Abstract: A pixel arrangement structure, a display substrate and a mask group are disclosed. The pixel arrangement structure includes a plurality of pixel groups, each of the plurality of pixel groups includes one red sub-pixel, two green sub-pixels and one blue sub-pixel; the red sub-pixel and the blue sub-pixel are arranged along a first direction; the two green sub-pixels are arranged along a second direction. Four vertexes included in the red sub-pixel are located in a first virtual rhombus and are substantially coincident with four vertexes of the first virtual rhombus, respectively; four vertexes included in the blue sub-pixel are located in a second virtual rhombus and are substantially coincident with four vertexes of the second virtual rhombus, respectively; at least one of the red or the blue sub-pixel has a shape of a corresponding virtual rhombus with each side of the virtual rhombus being an inwardly concaved side.

Abstract: A display panel and a display device are provided. The display panel includes: a substrate, a plurality of pixel units, a functional signal line, and a first conductive structure. The substrate includes a display area and a peripheral area on at least one side of the display area, the plurality of pixel units are in the display area, each pixel unit includes a light-emitting unit and a pixel circuit structure for providing a driving current to the light-emitting unit, and the light-emitting unit is an electroluminescent element. The functional signal line is connected with the pixel circuit structure of each pixel unit and provides a common voltage signal for the pixel circuit structure. The first conductive structure is connected in parallel with the functional signal line and is located at a layer different from that of the functional signal line.

Abstract: The present disclosure provides a display backplane, a method for manufacturing the same and a full-screen fingerprint identification display device. The display backplane includes a substrate; a circuit layer disposed on a surface of the substrate; a light emitting device layer disposed on a surface of the circuit layer away from the substrate; and a plurality of fingerprint identification photodetectors disposed in at least one of the circuit layer and the light emitting device layer.

Abstract: The present disclosure discloses an organic light emitting display device. The organic light emitting display device includes a substrate, an initializing voltage input line, a first electrode line, a thin film transistor, and an organic light emitting diode arranged on the substrate. The thin film transistor includes a first electrode, a second electrode and a control electrode, and the first electrode is coupled to the first electrode line, the initializing voltage input line is provided in the same layer and is made of the same material as one of the first electrode, the second electrode and the control electrode of the thin film transistor, and an extension direction of the initializing voltage input line is substantially the same as an extension direction of the first electrode line.

Abstract: An array substrate has a display area and a peripheral area located outside the display area. The display area includes two first sides that are substantially parallel and arc sides connected to ends of the first sides. The array substrate includes at least one gate driving circuit. Each gate driving circuit includes GOA units sequentially distributed along each arc side in at least one arc side and active GOA units sequentially distributed along a first side connected to the arc side. The GOA units includes at least one active GOA unit and at least one dummy GOA unit. Each active GOA unit is configured to provide a driving signal to at least one sub-pixel. A distance between two adjacent GOA units in the GOA units is approximately same as a distance between two adjacent active GOA units in the active GOA units.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: Embodiments of the disclosure provide a thin-film transistor, an array substrate, a display panel and a display device. The thin-film transistor includes a current enhancement portion, and the current enhancement portion is provided between a drain and a source. The current enhancement portion may include at least one protrusion portion, and the protrusion portion is provided on the drain and/or the source and faces a channel. The current enhancement portion may include an island portion provided between the drain and the source, and the island portion is separate from the drain and the source. The island portion may include at least one protrusion end, and the at least one protrusion end faces the drain and/or the source.

Abstract: The present disclosure relates to a shift register for a display panel. The shift register may include an input terminal, an output terminal, an input unit, an output unit, a first control unit, a second control unit, and a first isolation unit. The output unit may be configured to transmit a first level or a second level to an output terminal based on levels of a first node and a second node.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels, a first power line and an electrical connection layer on the base substrate. Each sub-pixel includes a pixel circuit, and a plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns along a first direction and a second direction. The sub-pixel is electrically connected with the light-emitting element through the electrical connection layer, and the portion, which is in the display region of the display substrate, of the electrical connection layer is not overlapped with the first power line in a direction perpendicular to the base substrate.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: Arrangements of the present disclosure relate to an array substrate, a display panel and a display device. The array substrate includes a circuit region and a boundary region. The circuit region includes a plurality of stacked conductive layers and an interlayer dielectric disposed between every two adjacent conductive layers. One or more first via holes are provided on the interlayer dielectric. The boundary region is disposed outside the circuit region. One or more second via holes for improving uniformity of the first via holes in the circuit region are disposed within a preset range of the boundary region close to one side of the circuit region. The second via holes and the first via holes are disposed on the same interlayer dielectric.

Abstract: A display panel and a display device are provided, the display panel includes a gate driving circuit, a first pixel module, and a second pixel module, the first pixel module includes a first pixel circuit, and the second pixel module includes a second pixel circuit; the gate driving circuit respectively provides corresponding gate driving signals for the first pixel circuit and the second pixel circuit; in the first display region, the number of columns of the pixel circuit included by the first pixel module is greater than the maximum number of columns of the pixel circuit included by the second pixel module in the second display region; the display panel further includes a loading structure arranged in a non-display region; the load structure is electrically connected to the gate wiring; the gate wiring is wiring between the gate driving circuit and the second pixel circuit for providing the corresponding gate driving signals to the second pixel circuit.

Abstract: The present disclosure relates to the field of display technologies, and provides a gamma circuit. The gamma circuit includes: a plurality of positive gamma voltage output terminals, a plurality of negative gamma voltage output terminals in one-to-one correspondence with the plurality of positive gamma voltage output terminals, and a plurality of voltage conversion circuits. Each of the voltage conversion circuits is configured to output a negative gamma reference voltage to the negative gamma voltage output terminal based on a positive gamma reference voltage output by the positive gamma voltage output terminal corresponding to the negative gamma voltage output terminal.

Abstract: The disclosure relates to a display panel and a display apparatus. The display panel comprises: a substrate comprising a substrate display region corresponding to a display panel display region and a substrate non-display region corresponding to a display panel non-display region; a non-display region circuit located at the substrate non-display region; and a packaging layer located on the non-display region circuit and having at least a partial overlap area with the non-display region circuit, wherein the non-display region circuit comprises: a first conductive pattern; at least one buffer layer located at a side of the first conductive pattern close to the substrate; at least one gate insulating layer configured to electrically insulate the first conductive pattern and other conductive patterns; and at least one interlayer insulating layer located at a side of the first conductive pattern away from the substrate.

Abstract: A pixel driving circuit, an array substrate and a display device are provided. The pixel driving circuit includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer is arranged on the side of a gate layer lead away from a base substrate and is formed with a first via hole exposing the gate layer lead. The second interlayer dielectric layer is arranged on the side of the first interlayer dielectric layer away from the base substrate and is formed with a second via hole exposing the first via hole. A source drain layer lead is arranged on the side of the second interlayer dielectric layer away from the base substrate and is electrically connected to the gate layer lead through the first via hole and the second via hole.

Abstract: The present disclosure provides a lead arrangement structure for an OLED display device and a display device. The lead arrangement structure is disposed on a substrate of the display device. The substrate includes a display region and a lead region surrounding the display region. The lead arrangement structure includes first power lines disposed in the display region and second power lines disposed in the lead region, wherein each of the first power lines is electrically connected to a plurality of columns of sub-pixels, and one end of each of the second power lines is connected to a connection terminal on the substrate and the other end of the second power line is electrically connected to a plurality of the first power lines. The lead arrangement structure for the OLED display device and the display device according to the present disclosure can reduce the wiring workload of the power line, improve the utilization rate of the pixel space, and improve the display effect.

Abstract: A display panel and a display device. The display panel includes a pixel circuit structure, a data line and a voltage signal line. The data line is connected to the pixel circuit structure to provide a data signal; the voltage signal line is connected to the pixel circuit structure to provide a voltage signal, the voltage signal is a constant voltage signal; the pixel circuit structure includes a first stabilization capacitor provided between the data line and the voltage signal line.

Abstract: A display device includes: a display panel; a housing configured to support and protect the display panel; a bracket disposed between the display panel and the housing; a plurality of sensors fixed on the bracket; a window located in the display panel or in the housing, and configured to expose at least one of the plurality of sensors; and a driver configured to control the bracket to rotate in a plane parallel to the display panel, and to control the bracket to stop rotating when a required sensor rotates to a position of the window.