Patents by Inventor Xuehong HE

Xuehong HE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240056698
    Abstract: The present invention is to provide an image signal detection circuit, a control method, and a motion detection method. The image signal detection circuit comprises at least one acquisition module, the acquisition module comprises at least one acquisition sub-module, the acquisition sub-module comprises a capacitor to acquire the difference between a pair of two consecutive frames of pixel signals by taking a reference voltage as a reference. The image signal detection circuit and a motion detection circuit are structurally simple and easy to implement. It can realize motion detection at increased difference detection speed without analog-to-digital conversion.
    Type: Application
    Filed: December 24, 2021
    Publication date: February 15, 2024
    Inventors: Xi ZENG, Xuehong HE
  • Patent number: 11611813
    Abstract: A method of removing fixed pattern noise, comprising: S01: performing a single-frame segmented exposure on a pixel array; S02: reading a of the pixel array, comprising: S021: performing a soft reset, so as to set the reset signal of the pixel unit to an intermediate voltage, and reading a differential reset signal; S022: performing a hard reset so as to set the reset signal of the pixel unit to a high voltage; S023: turning on a transmission MOS transistor to enable an exposure signal of to photodiode to transmitted to the floating diffusion area, and reading a differential pixel transmission signal; S03: subtracting the differential reset signal from the differential pixel transmission signal to obtain an exposure signal with fixed pattern noise removed. Another method is removing fixed pattern noise and an image sensor are further provided.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: March 21, 2023
    Assignee: SHANGHAI IC R&D CENTER CO., LTD
    Inventors: Xi Zeng, Pu Zhou, Huijie Yan, Ying Luo, Xuehong He, Yuan Zhang, Hailing Yang, Xiameng Lian
  • Publication number: 20220345650
    Abstract: A method of removing fixed pattern noise, comprising: S01: performing a single-frame segmented exposure on a pixel array; S02: reading a signal of the pixel array, comprising: S021: performing a soft reset, so as to set the reset signal of the pixel unit to an intermediate voltage, and reading a differential reset signal; S022: performing a hard reset so as to set the reset signal of the pixel unit to a high voltage; S023: turning on a transmission MOS transistor to enable an exposure signal of the photodiode to be transmitted to the floating diffusion area, and reading a differential pixel transmission signal; S03: subtracting the differential reset signal from the differential pixel transmission signal to obtain an exposure signal with fixed pattern noise removed. Another method of removing fixed pattern noise and an image sensor are further provided.
    Type: Application
    Filed: July 23, 2020
    Publication date: October 27, 2022
    Inventors: Xi ZENG, Pu ZHOU, Huijie YAN, Ying LUO, Xuehong HE, Yuan ZHANG, Hailing YANG, Xiameng LIAN
  • Patent number: 10673448
    Abstract: A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 2, 2020
    Assignees: SHANGHAI IC R&D CENTER CO., LTD, CHENGDU IMAGE DESIGN TECHNOLOGY CO., LTD.
    Inventors: Xuehong He, Changming Pi, Hailing Yang
  • Publication number: 20190268012
    Abstract: A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate.
    Type: Application
    Filed: November 22, 2017
    Publication date: August 29, 2019
    Inventors: Xuehong HE, Changming PI, Hailing YANG