Abstract: A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.

Abstract: A method and device for implementing end-to-end Hardware Message Passing (HMP) are disclosed. The device includes: a message memory, a controller, a message input interface and a message output interface. The message memory is configured to temporarily store a message. The controller is configured to perform management on a message in the form of hardware, store a message obtained from the message input interface into the message memory, and read a message from the message memory and transmit the message to a message user via the message output interface. The message input interface is directly connected with a message creator and is configured to obtain a message created by the message creator under the control of the controller. The message output interface is directly connected to the message and is configured to provide a message to the message user under the control of the controller. The disclosure can improve the efficiency of message passing and reduce software management overhead.

Abstract: The disclosure discloses an intelligence cache and an intelligence terminal, wherein the intelligence cache comprises: a general interface, configured to receive configuration information and/or control information, and/or data information from a core a bus, and return target data; a software define and reconfiguration unit configured to define a memory as a required cache memory according to the configuration information; a control unit, configured to control writing and reading of the cache memory and monitor instructions and data streams in real time; a memory unit, composed of a number of memory modules and configured to cache data; the required cache memory is formed by memory modules according to the definition of the software define and reconfiguration unit; and an intelligence processing unit, configured to process input and output data and transfer, convert and operate on data among multiple structures defined in the control unit.

Abstract: The disclosure discloses an intelligence cache and an intelligence terminal, wherein the intelligence cache comprises: a general interface, configured to receive configuration information and/or control information, and/or data information from a core a bus, and return target data; a software define and reconfiguration unit configured to define a memory as a required cache memory according to the configuration information; a control unit, configured to control writing and reading of the cache memory and monitor instructions and data streams in real time; a memory unit, composed of a number of memory modules and configured to cache data; the required cache memory is formed by memory modules according to the definition of the software define and reconfiguration unit; and an intelligence processing unit, configured to process input and output data and transfer, convert and operate on data among multiple structures defined in the control unit.

Abstract: A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.

Abstract: A method and system for multiple processors to share memory are disclosed. The method includes that: at least one local interconnection network is set, each of which is connected with at least two function modules; a local shared memory unit connected with the local interconnection network is set, and address space of each function module is mapped to the local shared memory unit; a first function module of the at least two function modules writes processed initial data into the local shared memory unit through the local interconnection network; and a second function module of the at least two function modules acquires data from the local shared memory unit via the local interconnection network. The technical solution of the disclosure can solve the drawbacks that a conventional system for multiple processors to globally share memory suffers a large transmission delay, high management overhead and the like.

Abstract: A method and device for implementing end-to-end Hardware Message Passing (HMP) are disclosed. The device includes: a message memory, a controller, a message input interface and a message output interface. The message memory is configured to temporarily store a message. The controller is configured to perform management on a message in the form of hardware, store a message obtained from the message input interface into the message memory, and read a message from the message memory and transmit the message to a message user via the message output interface. The message input interface is directly connected with a message creator and is configured to obtain a message created by the message creator under the control of the controller. The message output interface is directly connected to the message and is configured to provide a message to the message user under the control of the controller. The disclosure can improve the efficiency of message passing and reduce software management overhead.

Abstract: A method for configuring a service and a method and apparatus for rate matching in a TD-SCDMA system, this method for configuring the service includes: taking that a check bit puncturing ratio should be more than 7i+a or less than 7i?a as a newly added constraint condition, and the check bit puncturing ratios of each configured service being outside a range of [7i+a, 7i?a], the method for rate matching includes: when puncturing each path of check bits of the current data block, if a difference between a position Pk of kth reserved check bit calculated according to a method defined by the service and a previously determined position NPk?1 of k?1th reserved check bit is a positive integral multiple of 7, determining a position NPk of kth reserved check bit as Pk plus 1 or Pk minus 1, and Pk plus 1 and Pk minus 1 requiring carrying out alternately.

Abstract: A method for configuring a service and a method and apparatus for rate matching in a TD-SCDMA system, this method for configuring the service includes: taking that a check bit puncturing ratio should be more than 7i+a or less than 7i?a as a newly added constraint condition, and the check bit puncturing ratios of each configured service being outside a range of [7i+a, 7i?a], the method for rate matching includes: when puncturing each path of check bits of the current data block, if a difference between a position Pk of kth reserved check bit calculated according to a method defined by the service and a previously determined position NPk-1 of k?1th reserved check bit is a positive integral multiple of 7, determining a position NPk of kth reserved check bit as Pk plus 1 or Pk minus 1, and Pk plus 1 and Pk minus 1 requiring carrying out alternately.