Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Abstract: A memory device and associated techniques for reducing disturbs of select gate transistors and dummy memory cells in a memory device. In one approach, a ramp up of the voltage of a dummy word line is delayed relative to a ramp up of a voltage of data word lines in a program phase of a program loop, after a pre-charge phase of the program loop. Another possible approach delays the ramp up of a first dummy memory cell while the voltage of a second dummy memory cell is maintained at an elevated level throughout the pre-charge phase and the program phase. In another aspect, the disturb countermeasure is used when the selected data memory cell is relatively close to the source-end of the memory string and phased out when the selected data memory cell is relatively close to the drain-end of the memory string.

Abstract: A memory device and associated techniques for reducing disturbs of select gate transistors and dummy memory cells in a memory device. In one approach, a ramp up of the voltage of a dummy word line is delayed relative to a ramp up of a voltage of data word lines in a program phase of a program loop, after a pre-charge phase of the program loop. Another possible approach delays the ramp up of a first dummy memory cell while the voltage of a second dummy memory cell is maintained at an elevated level throughout the pre-charge phase and the program phase. In another aspect, the disturb countermeasure is used when the selected data memory cell is relatively close to the source-end of the memory string and phased out when the selected data memory cell is relatively close to the drain-end of the memory string.

Abstract: A three-dimensional stacked memory device provides uniform programming speeds for a block of memory cells. The channel layers of the memory strings which are relatively close to a local interconnect of a stack are doped to account for a reduced blocking oxide thickness. Channel layers of remaining memory strings are undoped. The doping can be performing by masking the channel layers which are to remain undoped while exposing the other memory holes to a dopant. The dopant can be provided, e.g., in a carrier gas, spin on glass or other solid, or by plasma doping. An n-type dopant such as antimony, arsenic or phosphorus may be used. Heating causes the dopants to diffuse into the channel layer. Another approach deposits doped silicon for some of the channel layers and undoped silicon for other channel layers.

Abstract: A three-dimensional stacked memory device provides uniform programming speeds for a block of memory cells. The channel layers of the memory strings which are relatively close to a local interconnect of a stack are doped to account for a reduced blocking oxide thickness. Channel layers of remaining memory strings are undoped. The doping can be performing by masking the channel layers which are to remain undoped while exposing the other memory holes to a dopant. The dopant can be provided, e.g., in a carrier gas, spin on glass or other solid, or by plasma doping. An n-type dopant such as antimony, arsenic or phosphorus may be used. Heating causes the dopants to diffuse into the channel layer. Another approach deposits doped silicon for some of the channel layers and undoped silicon for other channel layers.

Abstract: A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.

Abstract: A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.

Abstract: Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. However, there can be a variation in the endurance of cells even within a single die. By evaluating the dummy memory cells, an early warning can be obtained of a degradation of the data memory cells. Moreover, there is no interference with the operation of the data memory cells. Based on a number of dummy memory cells which have a Vth below a demarcation voltage, a corrective action is taken such as adjusting read voltages, an initial program voltage and/or an initial erase voltage, or marking the block as being bad and recovering the data.

Abstract: A three-dimensional stacked memory device provides uniform programming speeds for a block of memory cells. The channel layers of the memory strings which are relatively close to a local interconnect of a stack are doped to account for a reduced blocking oxide thickness. Channel layers of remaining memory strings are undoped. The doping can be performing by masking the channel layers which are to remain undoped while exposing the other memory holes to a dopant. The dopant can be provided, e.g., in a carrier gas, spin on glass or other solid, or by plasma doping. An n-type dopant such as antimony, arsenic or phosphorus may be used. Heating causes the dopants to diffuse into the channel layer. Another approach deposits doped silicon for some of the channel layers and undoped silicon for other channel layers.

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when the voltages of the drain and source ends of a memory string are increased to an erase level which charges up the channel. In one approach, the voltage of the word line which is adjacent to a select gate line is temporarily increased. Another approach builds off the first approach by temporarily increasing the voltage of the select gate line at the same time as the increase in the word line voltage.

Abstract: Apparatuses and techniques are described for temperature dependent erase in non-volatile storage. In one aspect, select gate voltage magnitude depends on temperature. This temperature dependent select gate voltage may be applied to a control gate of a select transistor while applying an erase voltage to a bit line and/or source line coupled to the select transistor. This can help assure that there is sufficient GIDL current for efficient erase at lower temperatures. In one aspect, a control circuit increases the duration of the erase voltage that is applied to the source line and/or the bit line at lower temperatures. In one aspect, the magnitude of the first erase voltage in a sequence depends on the present temperature.

Abstract: Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. However, there can be a variation in the endurance of cells even within a single die. By evaluating the dummy memory cells, an early warning can be obtained of a degradation of the data memory cells. Moreover, there is no interference with the operation of the data memory cells. Based on a number of dummy memory cells which have a Vth below a demarcation voltage, a corrective action is taken such as adjusting read voltages, an initial program voltage and/or an initial erase voltage, or marking the block as being bad and recovering the data.

Abstract: A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance.

Abstract: Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. In one aspect, a read pass voltage is discharged in a manner that purges residual electrons from a memory string channel after a sensing operation. A control circuit may begin to discharge the read pass voltage from memory cell control gates at different strategic times in order to provide a path for residual electrons to leave the channel. Because residual electrons have been purged from the channel, no or very few electrons will be trapped in shallow interface traps of the memory cell if the word line voltage does creep up following sensing. Thus, the word line voltage may still creep up after the sensing operation without changing a threshold voltage of the memory cell.

Abstract: Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. The word line creep up could cause electrons to trap in shallow interface traps of a memory cell, hence impacting its threshold voltage. In one aspect, trapped electrons are removed (e.g., de-trapped) from shallow interface traps of a memory cell using a weak erase operation. Therefore, problems associated with word line voltage creep up are reduced or prevented. Thus, the memory cell can be sensed without waiting, while still providing an accurate result. The weak erase could be part of a sensing operation, but that is not required. For example, the weak erase could be incorporated into the beginning part of a read operation, which provides for a very efficient solution.