Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU), a microcontroller, and a memory access unit. The AFU and the core share a plurality of virtual addresses to access a memory. The microcontroller is coupled between the core and the AFU. The core develops and stores a task in one of the virtual addresses. The microcontroller analyzes the task and dispatches the task to the AFU. The AFU accesses the virtual address indicating where the task is stored through the memory access unit to executes the task.

Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU) and an acceleration interface. The unit runs a plurality of processes and develops at least one task queue corresponding to each of the processes. The core generates several command packets and pushes them into the corresponding task queue. The AFU are used to execute the command packets. The acceleration interface is arranged between the AFU and the core to receive an acceleration interface instruction from the processing core, and establish a bit map based on the acceleration interface instruction. The bit map is used to indicate which task queue contains the command packets that have been generated.

Abstract: A processing system includes at least one core, a plurality of accelerator function unit (AFU) and a memory access unit. The memory access unit includes at least one pipeline resource and an arbitrator. The core develops a plurality of tasks. Each of the AFU is used to execute at least one of the tasks which corresponds to several memory access requests. The arbitrator selects one of the AFUs using a round-robin method at each clock period to transmit a corresponding memory access request of the selected AFU to the pipeline resource, so that the selected AFU executes the memory access request through the pipeline resource to read or write data related to the task.

Abstract: A processing system includes at least one core, several accelerator function units (AFU) and a microcontroller. The core is utilized to operate several processes and develop at least one task queue corresponding to each of the processes. The processing core generates several command packets and pushes them into the corresponding task queue. The AFU executes the command packets. The microcontroller is arranged between the AFU and the core to dispatch the command packet to a corresponding AFU for execution. When the corresponding AFU executes the command packet of a specific process of the processes, the microcontroller assigns the corresponding AFU to execute other command packets in the task queue of the specific process at a higher priority.

Abstract: Disclosed is an active inserted gastric tube with an intra-body communication function, including a tube body, a pulse module, an intra-body communication module and a control module. The pulse module is arranged at a front end of the tube body, and is configured to generate a pulse signal. the intra-body communication module is configured to receive the pulse signal generated by the pulse module and transmit the pulse signal to the control module. The control module is configured to analyze the received pulse signal. In this way, the pulse signal is generated by the pulse module, and the gastric tube is inserted into the esophagus through the tube body. The pulse signal is transmitted through a human body to realize an intra-body communication. The control module analyzes the pulse signal transmitted through the human body, so as to identify whether the tube body is inserted into the esophagus or trachea.

Abstract: A processing system includes a core, at least one accelerator function unit (AFU) and an accelerator interface. The core is utilized to develop at least one task. The AFU is utilized to execute the task. The accelerator interface is arranged between the core and the AFU to receive an accelerator interface instruction transmitted by the processing core and instruct the AFU to execute the task according to the accelerator interface instruction.

Abstract: A processing system includes a core, at least one accelerator function unit (AFU) and an accelerator interface. The core is utilized to develop at least one task. The AFU is utilized to execute the task. The accelerator interface is arranged between the core and the AFU to receive an accelerator interface instruction transmitted by the processing core and instruct the AFU to execute the task according to the accelerator interface instruction.

Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU) and an acceleration interface. The unit runs a plurality of processes and develops at least one task queue corresponding to each of the processes. The core generates several command packets and pushes them into the corresponding task queue. The AFU are used to execute the command packets. The acceleration interface is arranged between the AFU and the core to receive an acceleration interface instruction from the processing core, and establish a bit map based on the acceleration interface instruction. The bit map is used to indicate which task queue contains the command packets that have been generated.

Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU), a microcontroller, and a memory access unit. The AFU and the core share a plurality of virtual addresses to access a memory. The microcontroller is coupled between the core and the AFU. The core develops and stores a task in one of the virtual addresses. The microcontroller analyzes the task and dispatches the task to the AFU. The AFU accesses the virtual address indicating where the task is stored through the memory access unit to executes the task.

Abstract: A processing system includes at least one core, a plurality of accelerator function unit (AFU) and a memory access unit. The memory access unit includes at least one pipeline resource and an arbitrator. The core develops a plurality of tasks. Each of the AFU is used to execute at least one of the tasks which corresponds to several memory access requests. The arbitrator selects one of the AFUs using a round-robin method at each clock period to transmit a corresponding memory access request of the selected AFU to the pipeline resource, so that the selected AFU executes the memory access request through the pipeline resource to read or write data related to the task.

Abstract: A processing system includes at least one core, a plurality of accelerator function units (AFU) and a memory access unit. The memory access unit includes several schedulers and a pipeline resource. The core develops several tasks. Each AFU is used to execute one of the tasks correspondingly in association with memory several access requests. Each scheduler corresponds to each AFU for sorting the memory access requests based on the sequence in which the memory access requests were received from the corresponding AFU. The pipeline resource receives and executes memory access requests transmitted by the scheduler, and it transmits execution results of the memory access request to the corresponding AFU through each scheduler after executing the memory access request.

Abstract: A processing system includes at least one core, several accelerator function units (AFU) and a microcontroller. The core is utilized to operate several processes and develop at least one task queue corresponding to each of the processes. The processing core generates several command packets and pushes them into the corresponding task queue. The AFU executes the command packets. The microcontroller is arranged between the AFU and the core to dispatch the command packet to a corresponding AFU for execution. When the corresponding AFU executes the command packet of a specific process of the processes, the microcontroller assigns the corresponding AFU to execute other command packets in the task queue of the specific process at a higher priority.

Abstract: A balancing device, which is configured to balance a first duty cycle of a first accelerator and a second duty cycle of a second accelerator, includes a loading monitor and a loading balancer. The loading monitor is configured to monitor a first busy period of the first accelerator and a second busy period of the second accelerator. The loading balancer calculates the first duty cycle and the second duty cycle according to the first busy period and the second busy period, and moves at least one command queue of the first accelerator and the second accelerator according to the first duty cycle and the second duty cycle, such that the first duty cycle is close to the second duty cycle.

Abstract: A balancing device, which is configured to balance a first duty cycle of a first accelerator and a second duty cycle of a second accelerator, includes a loading monitor and a loading balancer. The loading monitor is configured to monitor a first busy period of the first accelerator and a second busy period of the second accelerator. The loading balancer calculates the first duty cycle and the second duty cycle according to the first busy period and the second busy period, and moves at least one command queue of the first accelerator and the second accelerator according to the first duty cycle and the second duty cycle, such that the first duty cycle is close to the second duty cycle.

Abstract: Provided is a Central Processing Unit (CPU) and a method to verify mainboard data. The CPU comprises: an on-die Read-Only Memory (ROM) for storing trusted root digest information, wherein the trusted root digest information is not allowed to be modified; and a core for, during a power-up process, computing digest information of a trusted root data stored in a mainboard using a digest algorithm, comparing the digest information with the trusted root digest information, and performing a signature verification algorithm with the trusted root data to verify the integrity of mainboard data if the digest information coincides with the trusted root digest information.

Abstract: Method and system for supplying emergency power to nuclear power plant, wherein the method includes, providing accumulator battery system, connected to emergency bus, the accumulator battery system is monitored by online monitoring system; in case of power loss of electrical devices of the nuclear power plant, the online monitoring system starts the accumulator battery system to provide power supply to the electrical devices of the nuclear power plant via the emergency bus. The present application is adapt to the key technologies and battery management technologies of million kilowatt-class advanced pressurized water reactor nuclear power plant, facilitating to improve the safety of the nuclear power plant in case of serious natural disasters beyond design working conditions.

Abstract: Method and system for supplying emergency power to nuclear power plant, wherein the method includes, providing accumulator battery system, connected to emergency bus, the accumulator battery system is monitored by online monitoring system; in case of power loss of electrical devices of the nuclear power plant, the online monitoring system starts the accumulator battery system to provide power supply to the electrical devices of the nuclear power plant via the emergency bus. The present application is adapt to the key technologies and battery management technologies of million kilowatt-class advanced pressurized water reactor nuclear power plant, facilitating to improve the safety of the nuclear power plant in case of serious natural disasters beyond design working conditions.