Abstract: A display substrate and a display device. The display substrate includes a base substrate, and a plurality of pixel units and a plurality of scanning lines on the base substrate. Each pixel unit includes a plurality of sub-pixels and a light shielding layer, the plurality of sub-pixels is arranged in sequence in a first direction, each sub-pixel includes a sub-pixel driving circuitry and a light-emitting element coupled to each other, and the sub-pixel driving circuitry is configured to provide a driving signal to the light-emitting element. At least a part of the light shielding layer is arranged between the sub-pixel driving circuitry and the base substrate. Each scanning line includes at least a part extending in the first direction, is coupled to a corresponding sub-pixel driving circuitry, and is arranged at a same layer as the light shielding layer.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first transmission circuit and a first input-output unit. The first transmission circuit is electrically connected to a blanking pull-up node and a first pull-up node. The first input-output unit includes an output circuit, a first pull-down control circuit, and a first pull-down auxiliary control circuit.

Abstract: A display panel includes: a substrate, sub-pixels and a gate drive circuit. The sub-pixel includes a pixel drive circuit. The gate drive circuit includes cascaded shift registers, and a shift register is electrically connected to pixel drive circuits in a row of sub-pixels. The gate drive circuit further includes cascade input signal lines and cascade display reset signal lines. The cascade input signal line is configured to connect a shift signal terminal and an input signal terminal of two different shift register; and the cascade display reset signal line is configured to connect a shift signal terminal and a display reset signal terminal of two different shift register. The display panel has sub-pixel regions for arranging the sub-pixels and first gap regions each located between two adjacent columns of sub-pixel regions; the cascade display reset signal lines and the cascade input signal lines are disposed in different first gap regions.

Abstract: Provided are a display panel, a driving method therefor and a display device. The display panel includes pixel driving circuits and a first gate driving circuit. The pixel driving circuit includes a driving circuit connected to first to third nodes for inputting a driving current to the third node through the second node, and a first switching unit having a first terminal connected to the third node and a second terminal connected to a sensing signal terminal for electrically connecting, in response to a signal at a control terminal thereof, the third node and sensing signal terminal. The first gate driving circuit includes a first output terminal corresponding to the pixel driving circuit and connected to the control terminal. The first output terminal outputs an active level pulse during data writing stage and black frame insertion stage of a driving cycle of the pixel driving circuit corresponding thereto.

Abstract: A shift register is provided and includes a display input reset circuit, an inverter circuit, at least one output circuit and a first detection circuit; the display input reset circuit, the inverter circuit and the output circuit are connected to a pull-up node; the inverter circuit and the at least one output circuit are connected to a pull-down node; the first detection circuit is connected to a signal acquisition point, an acquisition control terminal, and a first signal detection line, and configured to acquire a voltage at the signal acquisition point in response to a signal from the acquisition control terminal and output a detection voltage corresponding to the acquired voltage to the first signal detection line, an external first chip adjusts an active level voltage from the third power supply terminal according to the detection voltage; the signal acquisition point includes the pull-down node and/or a signal output terminal.

Abstract: A shift register includes a first scan unit, a leakage prevention unit, and a leakage prevention input unit. The first scan unit includes a first input circuit configured to transmit an input signal to a first pull-up node. The leakage prevention input unit is configured to: transmit a first voltage signal to a leakage prevention input node; and transmit a second voltage signal to the leakage prevention input node. The first voltage signal and the second voltage signal are different. The leakage prevention unit is configured to transmit one of the first voltage signal and the second voltage signal from the leakage prevention input node to a first leakage prevention node.

Abstract: Provided is an array substrate, including: a gate drive circuit disposed in a non-display region of a base substrate; a plurality of display pads disposed in a bonding region of the base substrate, wherein the plurality of display pads include gate drive signal pads, data signal pads, and voltage signal pads which are arranged in sequence in a first direction; and a plurality of gate connection wirings disposed in the non-display region of the base substrate, wherein a quantity of the gate connection wirings is greater than a quantity of the gate drive signal pads, wherein first ends of the gate connection wirings are electrically connected to the gate drive circuit, with second ends of one part of the gate connection wirings electrically connected to the gate drive signal pads and second ends of another part of the gate connection wirings electrically connected to the voltage signal pads.

Abstract: The disclosure provides a shift register unit, including: a sensing control circuit configured to write an active level signal to a sensing control node; a first sensing input circuit connected to a first pull-up back node and configured to write an active level signal to the first pull-up back node; a first display input circuit connected to a first pull-up node and configured to write an active level signal to the first pull-up node; a first switch circuit connected in series between the first pull-up node and the first pull-up back node and configured to control connection and disconnection between the first pull-up node and the first pull-up back node in response to control of a signal from a switch signal input terminal; and a first driving output circuit connected to the first pull-up back node and configured to write a signal to a first driving signal output terminal.

Abstract: The present disclosure provides a display device, a gate drive circuit, a shift register unit and a driving method thereof. The shift register unit includes an input subcircuit configured to control a voltage at the first node under voltage control of the input control end; a signal output subcircuit configured to control disconnection and conduction between the clock signal ends and respective signal output ends under voltage control of the first node; a first control subcircuit configured to control the voltage at the first node under voltage control of the first control signal end.

Abstract: A driving signal generation circuit includes a first node generation circuit, a second node generation circuit, a third node generation circuit, a first control node control circuit, a second control node control circuit and an output circuit; the second control node control circuit is configured to control to connect the second control node and the first clock signal terminal under the control of the potential of the second control node, and control the potential of the second control node according to the potential of the second node; the output circuit is configured to output corresponding driving signal through the driving signal output terminal under the control of the potential of the first control node and the potential of the second control node.

Abstract: Provided is a display device. The display device includes: a display panel and a control assembly; wherein the display panel includes a base substrate, a plurality of first color light-emitting units, and a sensing unit, wherein the sensing unit is electrically connected to the plurality of first color light-emitting units to acquire a plurality of sensing values; the control assembly is electrically connected to the sensing unit, and configured to acquire a plurality of rearranged sensing values by rearranging the plurality of sensing values; and the control assembly is further configured to adjust the plurality of first color light-emitting units in the display panel based on the plurality of rearranged sensing values.

Abstract: Provided are a display panel and a display apparatus, the display panel includes a substrate and a drive circuit layer, wherein the drive circuit layer includes a pixel circuit (P) arranged in an array, a plurality of first scan signal lines (G1) and a plurality of second scan signal lines (G2). The drive circuit layer includes a plurality of first discharge structures (E1) and/or a plurality of second discharge structures (E2). At least one first discharge structure (E1) is electrically connected to a first scan signal line (G1) and a second scan signal line (G2) respectively, and the first scan signal line (G1) and the second scan signal line (G2) electrically connected to the first discharge structure (E1) are electrically connected to the same row of pixel circuit.

Abstract: A scan circuit is provided. The scan circuit includes a random addressing circuit and a plurality of scan units. The random addressing circuit is configured to receive 2k number of control signals, and is configured to select at least one scan unit for outputting signals based on the 2k number of control signals. The plurality of scan units includes a plurality of scan unit groups. A respective scan unit group of the plurality of scan unit groups includes m number of scan units, and is configured to receive n number of clock signals. A respective scan unit of the m number of scan units in the respective scan unit group is configured to receive n? number of clock signals, n?<n, n? and n being positive integers. At least two scan units of the m number of scan units are configured to receive different combinations of clock signals.

Abstract: A shift register unit, a display driving circuit, a display panel, and a control method. The shift register unit includes: an input circuit configured to provide signals of an input signal terminal (IN) and a power signal terminal (VGH) to first and second pull-up nodes (Q1, Q2); a first control circuit configured to control potentials of the first pull-down node (QB1), and the first pull-up node (Q1); a second control circuit configured to control potentials of the second pull-up node (Q2) and the second pull-down node (QB2) based on the first pull-up node (Q1) and the first pull-down node (QB1); and an output circuit configured to provide the signal of one of the power signal terminal (VGH) and the reference signal terminal (VGL) to an output signal terminal (OUT) under control of the second pull-up node (Q2) and the second pull-down node (QB2).

Abstract: A shift register is provided to include a voltage control circuit coupled to an output control node; at least one driving output circuit, each including an output transistor and a capacitor structure sequentially arranged along a first direction; a first conductive line therebetween and extending along a second direction and coupled to a signal output line configured for the driving output circuit; the output transistor includes a gate electrode coupled to the output control node and a first voltage writing electrode of the capacitor structure, a first electrode coupled to a clock signal line configured for the driving output circuit and a second electrode coupled to the first conductive line; a second conductive line is disposed between the first conductive line and the capacitor structure, and the first conductive line is coupled to a second voltage writing electrode of the capacitor structure through the second conductive line.

Abstract: A shift register circuit includes an input sub-circuit, an output sub-circuit and a control sub-circuit. The input sub-circuit is coupled to a first input signal terminal and a pull-up node, and configured to, under control of a first input signal, transmit the first input signal to the pull-up node. The output sub-circuit is at least coupled to the pull-up node, a first clock signal terminal and a first signal output terminal, and configured to transmit a first clock signal to the first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is coupled to at least one first reference node, at least one first control signal terminal and the pull-up node, and configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal.

Abstract: A display substrate and a display device. The display substrate comprises: a base substrate, and a gate driving circuit and a plurality of sub-pixels arranged on the base substrate; the display substrate further comprises a heat dissipation hole structure, and at least part of an orthographic projection of the heat dissipation hole structure onto the base substrate is located between an orthographic projection of the gate driving circuit onto the base substrate and an orthographic projection of the sub-pixels onto the base substrate.

Abstract: A shift resister includes a first scan unit and a black insertion circuit. The first scan unit includes a first input circuit and a first output circuit. The first input circuit is configured to transmit a display input signal to a first pull-up node. The first output circuit is configured to, in a case where the first input circuit transmits the display input signal to the first pull-up node, transmit a first clock signal to a first scan signal terminal. The black insertion circuit is configured to transmit a black insertion input signal to the first pull-up node. The first output circuit is further configured to, in a case where the black insertion circuit transmits the black insertion input signal to the first pull-up node, transmit the first clock signal to the first scan signal terminal.

Abstract: A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node, wherein the second input sub-circuit includes an isolation sub-circuit, wherein the isolation sub-circuit is set between the first node and the blank-control node; an output sub-circuit configured to output signal under control of the first node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point. The anti-leak sub-circuit includes a second anti-leak transistor connected to the isolation sub-circuit.

Abstract: A display substrate includes a plurality of pixel circuits, and the pixel circuits each include a sensing circuit and a light-emitting control circuit. In a second direction, adjacent three rows of pixel circuits are a first row of pixel circuits, a second row of pixel circuits and a third row of pixel circuits. A region between the first row of pixel circuits and the second row of pixel circuits is a first gap region. In the first row of pixel circuits and the second row of pixel circuits, a sensing circuit of each pixel circuit is closer to the first gap region than a light-emitting control circuit of the pixel circuit, and sensing signal terminals of sensing circuits of two pixel circuits in a same column are a same signal terminal.