Patents by Inventor Xuejie Shi
Xuejie Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11605726Abstract: A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region.Type: GrantFiled: April 9, 2021Date of Patent: March 14, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Hansu Oh, Pengchong Li, Xuejie Shi, Yiyu Chen, Bo Su
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Publication number: 20220199808Abstract: A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region.Type: ApplicationFiled: April 9, 2021Publication date: June 23, 2022Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Hansu OH, Pengchong LI, Xuejie SHI, Yiyu CHEN, Bo SU
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Publication number: 20220199460Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, a dummy gate structure, a source-drain doped region, and an interlayer dielectric layer; removing the dummy gate structure located at an isolation region to form an isolation opening; performing first ion doping on a fin below the isolation opening, to form an isolation doped region, where a doping type of the isolation doped region is different from a doping type of the source-drain doped region; filling an isolation structure in the isolation opening; removing the remaining dummy gate structure, to form a gate opening; and forming a gate structure in the gate opening.Type: ApplicationFiled: November 8, 2021Publication date: June 23, 2022Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Pengchong LI, Xuejie SHI, Hansu OH, Bo SU
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Patent number: 10340304Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.Type: GrantFiled: June 26, 2018Date of Patent: July 2, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Dae-Sub Jung, Deyan Chen, Xuejie Shi
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Publication number: 20180308893Abstract: The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.Type: ApplicationFiled: June 26, 2018Publication date: October 25, 2018Inventors: Dae-Sub JUNG, Deyan CHEN, Xuejie SHI
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Patent number: 10038027Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region; forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.Type: GrantFiled: January 3, 2017Date of Patent: July 31, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Dae-Sub Jung, Deyan Chen, Xuejie Shi
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Publication number: 20170200758Abstract: The present disclosure provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region: forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.Type: ApplicationFiled: January 3, 2017Publication date: July 13, 2017Applicant: Semiconductor Manufacturing International (Beijing)Inventors: Dae-Sub JUNG, Deyan CHEN, Xuejie SHI
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Patent number: 8088676Abstract: Crystallization-inducing metal elements are introduced onto an amorphous silicon thin film. A first, low-temperature, heat-treatment induces nucleation of metal-induced crystallization (MIC), resulting in the formation of small polycrystalline silicon “islands”. A metal-gettering layer is formed on the resulting partially crystallized thin film. A second, low-temperature, heat-treatment completes the MIC process, whilst gettering metal elements from the partially crystallized thin film. The process results in the desired polycrystalline silicon thin film.Type: GrantFiled: April 27, 2006Date of Patent: January 3, 2012Assignee: The Hong Kong University of Science and TechnologyInventors: Man Wong, Hoi-Sing Kwok, Zhiguo Meng, Dongli Zhang, Xuejie Shi
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Publication number: 20060263957Abstract: Crystallization-inducing metal elements are introduced onto an amorphous silicon thin film. A first, low-temperature, heat-treatment induces nucleation of metal-induced crystallization (MIC), resulting in the formation of small polycrystalline silicon “islands”. A metal-gettering layer is formed on the resulting partially crystallized thin film. A second, low-temperature, heat-treatment completes the MIC process, whilst gettering metal elements from the partially crystallized thin film. The process results in the desired polycrystalline silicon thin film.Type: ApplicationFiled: April 27, 2006Publication date: November 23, 2006Applicant: The Hong Kong University of Science and TechnologyInventors: Man Wong, Hoi-Sing Kwok, Zhiguo Meng, Dongli Zhang, Xuejie Shi