Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

Abstract: A device includes sidewalls formed in a wafer surface, where the sidewalls descend to a recessed surface. The recessed surface generally promotes resist coverage on the wafer surface, including corners (e.g., junctions between the wafer surface and various surface topographies, such as cavities, the recessed surface, and so forth) on the wafer. In one or more implementations, a wet etching procedure is used to form the sidewalls and recessed surface. A resist material (e.g., a photoresist material) is deposited onto the wafer surface, where the photoresist fully covers one or more of the top corners of the wafer surface. In one or more implementations, the recessed surface is positioned adjacent a trench formed in the wafer to promote resist coverage on the top surface of the wafer.

Abstract: A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.

Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.

Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.

Abstract: A device includes sidewalls formed in a wafer surface, where the sidewalls descend to a recessed surface. The recessed surface generally promotes resist coverage on the wafer surface, including corners (e.g., junctions between the wafer surface and various surface topographies, such as cavities, the recessed surface, and so forth) on the wafer. In one or more implementations, a wet etching procedure is used to form the sidewalls and recessed surface. A resist material (e.g., a photoresist material) is deposited onto the wafer surface, where the photoresist fully covers one or more of the top corners of the wafer surface. In one or more implementations, the recessed surface is positioned adjacent a trench formed in the wafer to promote resist coverage on the top surface of the wafer.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.

Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.

Abstract: A micro relay of a micro-electro-mechanical system (MEMS), includes a cap substrate, a first electrical contact, an actuator, and a second electrical contact. The first electrical contact is formed on the cap substrate, includes a platinum group metal, and includes a first surface layer of an oxide of the platinum group metal. The second electrical contact is formed on the actuator, includes the platinum group metal, and includes a second surface layer of the oxide of the platinum group metal. At least a first portion of the first surface layer contacts at least a second portion of the second surface layer during cycling of the micro relay.

Abstract: Optical components may be integrated into planar light circuits. For example, thin film filters may be integrated through trenches in planar light circuits to achieve demultiplexing of at least two multiplexed optical wavelengths. An optical waveguide may be interfaced with a laser or a light detector through a mode converter formed as a trench in the planar light circuit. The mode converter may have a curved surface to achieve mode conversion.

Abstract: Optical components may be integrated into planar light circuits. For example, thin film filters may be integrated through trenches in planar light circuits to achieve demultiplexing of at least two multiplexed optical wavelengths. An optical waveguide may be interfaced with a laser or a light detector through a mode converter formed as a trench in the planar light circuit. The mode converter may have a curved surface to achieve mode conversion.