Patents by Inventor Xuejun Ying

Xuejun Ying has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240317832
    Abstract: An unnatural amino acid may have a structure as shown in formula (1) or may be an enantiomer thereof: Such unnatural amino acid may be used, e.g., in recombinant proteins. A recombinant protein may contain such unnatural amino acid and a protein conjugate prepared from the recombinant protein. The unnatural amino acid can be simple and convenient to prepare, safe in nature, difficult to inactivate when inserted into a protein, and may have a high binding rate with a coupling moiety, and the obtained conjugate is higher in stability. The unnatural amino acid is applicable to numerous fields, especially in preparation of a recombinant protein or a recombinant protein conjugate.
    Type: Application
    Filed: July 29, 2021
    Publication date: September 26, 2024
    Applicant: NOVOCODEX BIOPHARMACEUTICALS CO., LTD.
    Inventors: Jinwei YANG, Chenghao YE, Gang XIA, Pengchao HUO, Wen DING, Longfei CHEN, Lin JIAO, Hao HUANG, Xin HENG, Jingjing ZHU, Yuebin YING, Xuejun LIANG
  • Publication number: 20240245609
    Abstract: The present invention provides a freeze-dried composition containing anti-HER2 drug conjugate, which comprises ARX788 and one or more of pharmaceutically acceptable lyoprotectant, buffer salts and surfactants, wherein the pH value of the freeze-dried composition is from 5.7 to 6.3. The present invention also provides a freeze-dried preparation containing anti-HER2 drug conjugate and the preparation method thereof. The present invention also provides use of the freeze-dried composition and the freeze-dried preparation. The freeze-dried composition and the freeze-dried preparation provided by the present invention have a very excellent stability, as well as good appearance, short reconstitution time and low moisture content. The product quality is safe and reliable, and the production efficiency is high.
    Type: Application
    Filed: July 20, 2021
    Publication date: July 25, 2024
    Applicant: NOVOCODEX BIOPHARMACEUTICALS CO., LTD.
    Inventors: Lihai XIAO, Jiali CHEN, Moutian YE, Gang XIA, Jingjing ZHU, Lei FANG, Yuebin YING, Luxiong YE, Xuejun LIANG
  • Patent number: 9659900
    Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: May 23, 2017
    Assignee: Maxim Intergrated Products, Inc.
    Inventors: Xuejun Ying, Arkadii V. Samoilov, Peter McNally, Tyler Parent
  • Patent number: 9331048
    Abstract: A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 3, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Publication number: 20160079197
    Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 17, 2016
    Inventors: Xuejun Ying, Arkadii V. Samoilov, Peter McNally, Tyler Parent
  • Patent number: 9196587
    Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Xuejun Ying, Arkadii V. Samoilov, Peter McNally, Tyler Parent
  • Patent number: 9105750
    Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: August 11, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Arkadii V. Samoilov, Tyler Parent, Xuejun Ying
  • Patent number: 9040386
    Abstract: A device includes sidewalls formed in a wafer surface, where the sidewalls descend to a recessed surface. The recessed surface generally promotes resist coverage on the wafer surface, including corners (e.g., junctions between the wafer surface and various surface topographies, such as cavities, the recessed surface, and so forth) on the wafer. In one or more implementations, a wet etching procedure is used to form the sidewalls and recessed surface. A resist material (e.g., a photoresist material) is deposited onto the wafer surface, where the photoresist fully covers one or more of the top corners of the wafer surface. In one or more implementations, the recessed surface is positioned adjacent a trench formed in the wafer to promote resist coverage on the top surface of the wafer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 26, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Xuejun Ying, Li Li, Amit S. Kelkar, Brian S. Poarch
  • Publication number: 20150132891
    Abstract: A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 14, 2015
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Patent number: 8970043
    Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: March 3, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Patent number: 8963287
    Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Lei Tian, Scott W. Barry, Xuejun Ying
  • Publication number: 20150028455
    Abstract: A device includes sidewalls formed in a wafer surface, where the sidewalls descend to a recessed surface. The recessed surface generally promotes resist coverage on the wafer surface, including corners (e.g., junctions between the wafer surface and various surface topographies, such as cavities, the recessed surface, and so forth) on the wafer. In one or more implementations, a wet etching procedure is used to form the sidewalls and recessed surface. A resist material (e.g., a photoresist material) is deposited onto the wafer surface, where the photoresist fully covers one or more of the top corners of the wafer surface. In one or more implementations, the recessed surface is positioned adjacent a trench formed in the wafer to promote resist coverage on the top surface of the wafer.
    Type: Application
    Filed: December 27, 2013
    Publication date: January 29, 2015
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Xuejun Ying, Li Li, Amit S. Kelkar, Brian S. Poarch
  • Publication number: 20140264844
    Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.
    Type: Application
    Filed: June 28, 2013
    Publication date: September 18, 2014
    Inventors: Xuejun Ying, Arkadii V. Samoilov, Peter McNally, Tyler Parent
  • Patent number: 8742574
    Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: June 3, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Arkadii V. Samoilov, Tyler Parent, Xuejun Ying
  • Patent number: 8487405
    Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 16, 2013
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Lei Tian, Scott Wilson Barry, Xuejun Ying
  • Publication number: 20130037948
    Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Arkadii V. Samoilov, Tyler Parent, Xuejun Ying
  • Publication number: 20120211865
    Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.
    Type: Application
    Filed: February 17, 2011
    Publication date: August 23, 2012
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: LEI TIAN, SCOTT WILSON BARRY, XUEJUN YING
  • Publication number: 20120193808
    Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.
    Type: Application
    Filed: February 1, 2011
    Publication date: August 2, 2012
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Publication number: 20120194306
    Abstract: A micro relay of a micro-electro-mechanical system (MEMS), includes a cap substrate, a first electrical contact, an actuator, and a second electrical contact. The first electrical contact is formed on the cap substrate, includes a platinum group metal, and includes a first surface layer of an oxide of the platinum group metal. The second electrical contact is formed on the actuator, includes the platinum group metal, and includes a second surface layer of the oxide of the platinum group metal. At least a first portion of the first surface layer contacts at least a second portion of the second surface layer during cycling of the micro relay.
    Type: Application
    Filed: February 1, 2011
    Publication date: August 2, 2012
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Uppili Sridhar, Quanbo Zou, Amit S. Kelkar, Xuejun Ying
  • Lid
    Patent number: D985999
    Type: Grant
    Filed: January 23, 2021
    Date of Patent: May 16, 2023
    Inventor: Xuejun Ying