Abstract: Embodiments of the present disclosure provide a delay chain circuit and an electronic device. The delay chain circuit includes a delay branch, an inverting processing branch and a glitch elimination branch. The delay branch receives an input signal to obtain a first delayed signal and a second delayed signal. The inverting processing branch receives the first delayed signal to obtain a third delayed signal, and receives the second delayed signal to obtain a fourth delayed signal. The glitch elimination branch combines the third delayed signal and the fourth delayed signal to obtain a combined signal, and inverts the combined signal to obtain an output signal. The electronic device includes the delay chain circuit.

Abstract: A method and apparatus for timing training on an LVDS interface includes sampling by using the second parallel data as reference data and the first parallel data as scanning data, the first delay stage is obtained; sampling by using the first parallel data as reference data and the second parallel data as scanning data, and setting the initial delay stage of the second parallel data as the first delay stage, the second delay stage is obtained, and setting the sum of the first delay stage and half of the delay stage difference as the delay stage of the first parallel data, then receiving the LVDS differential data. The method is capable of handling the impact of OCV and asymmetry in signal slopes on the effective data window, avoiding glitches, and reducing the requirements for delay chain design.

Abstract: A parallel finite field multiplication device is disclosed. The device comprises M cascaded logic processing modules, each of which comprises four input ends and two output ends for carrying out different finite multiplication in different length. The device is calculated step by step through M cascaded logic processing modules according to the number of cascaded logic processing modules. In this device, M cascaded logic processing modules may be used, according to different numbers of the cascaded logic processing modules, in finite field multiplication of different lengths, without needing to carry out polynomial multiplication.