Abstract: An integrated circuit (IC) structure includes a plurality of cell rows with each cell row including a plurality of (standard) cells. A power rail for at least one pair of adjacent cell rows is asymmetric relative to a cell boundary between adjacent cells of the at least one pair of adjacent cell rows. Embodiments of the disclosure can also include the standard cell including a plurality of transistors at a device layer, and at least a portion of an isolation area at an edge of the device layer defining a cell boundary. The standard cell also includes the power rail including a first portion within the cell boundary and a second portion outside the cell boundary. The first portion and the second portion have different heights such that the power rail is asymmetric across the cell boundary. The asymmetric power rail provides seamless integration of cell libraries having different heights.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture. The structure includes a first contact connected in a cross couple circuit to at least two gate structures, and a second contact connected to the first contact at a location which is devoid of any via connection.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to local interconnect power rails merged with upper power rails and methods of manufacture. The structure includes: an active cell including contacts enclosed in active regions; at least one local interconnect power rail connecting to the contacts of the active regions; and at least one power rail above and connected to the at least one local interconnect power rail.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

Abstract: Methods of patterning metallization lines having variable widths in a metallization layer. A first mandrel layer is formed over a mask layer, with the mask layer overlying a second mandrel layer. The first mandrel layer is etched to form mandrel lines that have variable widths. The first non-mandrel trenches are etched in the mask layer, where the non-mandrel trenches have variable widths. The first mandrel lines are used to etch mandrel trenches in the mask layer, so that the mandrel lines and first non-mandrel lines define a mandrel pattern. The second mandrel layer is etched according to the mandrel pattern to form second mandrel lines, with the second mandrel lines having the variable widths of the plurality of first mandrel lines and the variable widths of the plurality of non-mandrel trenches.

Abstract: The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.

Abstract: Methods of patterning metallization lines having variable widths in a metallization layer. A first mandrel layer is formed over a mask layer, with the mask layer overlying a second mandrel layer. The first mandrel layer is etched to form mandrel lines that have variable widths. The first non-mandrel trenches are etched in the mask layer, where the non-mandrel trenches have variable widths. The first mandrel lines are used to etch mandrel trenches in the mask layer, so that the mandrel lines and first non-mandrel lines define a mandrel pattern. The second mandrel layer is etched according to the mandrel pattern to form second mandrel lines, with the second mandrel lines having the variable widths of the plurality of first mandrel lines and the variable widths of the plurality of non-mandrel trenches.

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: One illustrative method disclosed includes, among other things, forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure, wherein an upper surface of each of these contact structures are positioned at a first level. In one example, this method also includes forming a masking layer that covers the initial CB gate contact structure and exposes the initial GSD contact structure and, with the masking layer in position, performing a recess etching process on the initial GSD contact structure so as to form a recessed GSD contact structure, wherein a recessed upper surface of the recessed GSD contact structure is positioned at a second level that is below the first level.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

Abstract: One aspect of the disclosure is directed to a method of forming an integrated circuit structure. The method may include: providing a set of fins over a semiconductor substrate, the set of fins including a plurality of working fins and a plurality of dummy fins, the plurality of dummy fins including a first subset of dummy fins within a pre-defined distance from any of the plurality of working fins, and a second subset of dummy fins beyond the pre-defined distance from any of the plurality of working fins; removing the first subset of dummy fins by an extreme ultraviolet (EUV) lithography technique; and removing at least a portion of the second subset of dummy fins.

Abstract: The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.

Abstract: A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate. A plurality of substantially parallel metal lines are disposed in the dielectric layer. The metal lines include active lines for routing signals to and from the devices, and dummy lines which do not route signals to and from the devices. Signal cuts are disposed in the active lines. The signal cuts define tips of the active lines. Assist cuts are disposed exclusively in the dummy lines and do not define tips of the active lines. The assist cuts are located proximate the signal cuts such that a first density of assist cuts and signal cuts in an area surrounding the signal cuts is substantially greater than a second density of signal cuts alone in the same area.