Abstract: A complex computing device, a complex computing method, an artificial intelligence chip and an electronic apparatus are provided. An input interface receives complex computing instructions and arbitrates each complex computing instruction to a corresponding computing component respectively, according to the computing types in the respective complex computing instructions Each computing component is connected to the input interface, acquires a source operand from a complex computing instruction to perform complex computing, and generates a computing result instruction to feed back to an output interface. The output interface arbitrates the computing result in each computing result instruction to the corresponding instruction source respectively, according to the instruction source identifier in each computing result instruction.

Abstract: Example embodiments of the present application provide an instruction executing method and apparatus, an electronic device, and a computer-readable storage medium that may be applied in the field of artificial intelligence. The instruction executing method may include: executing an instruction sequence that includes memory instructions and non-memory instructions, the instructions in the sequence executed starting to be executed in order; determining that execution of a first memory instruction needs to be completed before a second memory instruction starts to be executed, the second memory instruction being a next memory instruction following the first memory instruction in the instruction sequence; and executing non-memory instructions between the first memory instruction and the second memory instruction without executing the second memory instruction, during a cycle of executing the first memory instruction.

Abstract: The disclosure discloses a method for executing instructions, a device and a computer readable storage medium. The detailed implementation includes: obtaining a first memory access instruction for execution, in which the first memory access instruction includes a first address range of a memory to be accessed; in response to detecting a predetermined instruction for monitoring an accessed address range of the memory, executing the predetermined instruction to obtain a remaining address range not accessed by the first memory access instruction in the first address range; comparing the remaining address range with a second address range included in a second memory access instruction to be executed; and suspending execution of the second memory access instruction in response to the remaining address range at least partially overlapping with the second address range.

Abstract: A method of executing an operation in a deep learning training, an electronic device, and a computer-readable storage medium, which relate to a field of artificial intelligence, especially to a field of deep learning. The method of executing an operation in a deep learning training includes: acquiring an instruction for the operation including a plurality of vector operations; determining, for each vector operation of the plurality of vector operations, two source operand vectors for a comparison; and executing the vector operation on the two source operand vectors using an instruction format for the vector operation, so as to obtain an operation result including a destination operand vector.

Abstract: A method and an apparatus for authenticating a chip are provided and a computer storage medium is also provided. The method may include configuring a software environment and a hardware environment associated with the chip via a configuration file, the configuration file including a plurality of instructions and data required to execute the instructions, the software environment and the hardware environment being created based on the chip; causing a plurality of instructions to be executed in a software environment and a hardware environment, respectively; obtaining a first information generated by executing instructions in a software environment and a second information generated by executing instructions in the hardware environment, respectively, the first information and the second information including the plurality of instructions being executed, its address, and data generated by executing the instructions; and authenticating the chip based on the generated first information and second information.

Abstract: An instruction prefetching method, a device and a medium are provided. The method includes the following: instructions in a target buffer are precompiled before a processor core fetches a required instruction from the target buffer corresponding to the processor core; if it is determined that a jump instruction exists in the target buffer and a jump target instruction corresponding to the jump instruction is not cached in the target buffer according to a precompiled result, the jump target instruction is prefetched from an icache into a candidate buffer corresponding to the processor core to wait for the processor core to fetch the jump target instruction from the candidate buffer; the target buffer and the candidate buffer are alternately reused during instruction prefetching.

Abstract: A caching device, an instruction cache, a system for processing an instruction, a method and apparatus for processing data and a medium are provided. The caching device includes a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a press-in port. The is configured to write cache data into a set storage address in the first queue and/or the second queue; the read port is configured to read all cache data from the first queue and/or the second queue at one time; the press-in port is configured to press cache data into the first queue and/or the second queue; the first pop-up port is configured to pop up cache data from the first queue; and the second pop-up port is configured to pop up cache data from the second queue.

Abstract: The present application discloses a complex computing device, a complex computing method, an artificial intelligence chip and an electronic apparatus, and relates to a field of artificial intelligence chips. One of the solutions includes: an input interface receives complex computing instructions and arbitrates each complex computing instruction to a corresponding computing component respectively, according to the computing types in the respective complex computing instructions; each computing component is connected to the input interface, acquires a source operand from a complex computing instruction to perform complex computing, and generates computing result instruction to feed back to an output interface; the output interface arbitrates the computing result in each computing result instruction to the corresponding instruction source respectively, according to the instruction source identifier in each computing result instruction.

Abstract: Embodiments of the present disclosure relate to a data access method and apparatus, an electronic device, and a computer-readable storage medium. The method may include, in response to receiving a first access request sent from a first access device in a set of access devices to a first storage device in a set of storage devices, sending an updated first access request to the first storage device, the first access request including identity information of the first access device. The method may further include, in response to receiving data from the set of storage devices, determining identity information included in the data. The method may further include, in response to the determined identity information being corresponding to the identity information of the first access device, sending the data to the first access device.

Abstract: The disclosure discloses a method for executing instructions, a device and a computer readable storage medium. The detailed implementation includes: obtaining a first memory access instruction for execution, in which the first memory access instruction includes a first address range of a memory to be accessed; in response to detecting a predetermined instruction for monitoring an accessed address range of the memory, executing the predetermined instruction to obtain a remaining address range not accessed by the first memory access instruction in the first address range; comparing the remaining address range with a second address range included in a second memory access instruction to be executed; and suspending execution of the second memory access instruction in response to the remaining address range at least partially overlapping with the second address range.

Abstract: The invention discloses an apparatus and method for writing back an instruction execution result. The apparatus for writing back the instruction execution result includes: a first writing port, coupled between a first execution unit with a first execution delay and a register file, and configured to receive a first execution result from the first execution unit, and to write the first execution result back to a first register unit in the register file based on a first writing address; and a second writing port, coupled between a second execution unit with a second execution delay different from the first execution delay and the register file, and configured to receive a second execution result from the second execution unit, and to write the second execution result back to a second register unit in the register file based on a second writing address.

Abstract: Example embodiments of the present application provide an instruction executing method and apparatus, an electronic device, and a computer-readable storage medium that may be applied in the field of artificial intelligence. The instruction executing method may include: executing an instruction sequence that includes memory instructions and non-memory instructions, the instructions in the sequence executed starting to be executed in order; determining that execution of a first memory instruction needs to be completed before a second memory instruction starts to be executed, the second memory instruction being a next memory instruction following the first memory instruction in the instruction sequence; and executing non-memory instructions between the first memory instruction and the second memory instruction without executing the second memory instruction, during a cycle of executing the first memory instruction.

Abstract: A caching device, an instruction cache, a system for processing an instruction, a method and apparatus for processing data and a medium are provided. The caching device includes a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a press-in port. The is configured to write cache data into a set storage address in the first queue and/or the second queue; the read port is configured to read all cache data from the first queue and/or the second queue at one time; the press-in port is configured to press cache data into the first queue and/or the second queue; the first pop-up port is configured to pop up cache data from the first queue; and the second pop-up port is configured to pop up cache data from the second queue.

Abstract: A method and an apparatus for authenticating a chip are provided and a computer storage medium is also provided. The method may include configuring a software environment and a hardware environment associated with the chip via a configuration file, the configuration file including a plurality of instructions and data required to execute the instructions, the software environment and the hardware environment being created based on the chip; causing a plurality of instructions to be executed in a software environment and a hardware environment, respectively; obtaining a first information generated by executing instructions in a software environment and a second information generated by executing instructions in the hardware environment, respectively, the first information and the second information including the plurality of instructions being executed, its address, and data generated by executing the instructions; and authenticating the chip based on the generated first information and second information.

Abstract: The present disclosure discloses an instruction prefetching method, a device and a medium. The present disclosure relates to a data storage technology, the method includes the following. Instructions in a target buffer are precompiled before a processor core fetches a required instruction from the target buffer corresponding to the processor core; if it is determined that a jump instruction exists in the target buffer and a branch instruction corresponding to the jump instruction is not cached in the target buffer according to a precompiled result, the branch instruction is prefetched from an icache into a candidate buffer corresponding to the processor core to wait for the processor core to fetch the branch instruction from the candidate buffer; the target buffer and the candidate buffer are alternately reused during instruction prefetching.

Abstract: Embodiments of the present disclosure relate to a data access method and apparatus, an electronic device, and a computer-readable storage medium. The method may include, in response to receiving a first access request sent from a first access device in a set of access devices to a first storage device in a set of storage devices, sending an updated first access request to the first storage device, the first access request including identity information of the first access device. The method may further include, in response to receiving data from the set of storage devices, determining identity information included in the data. The method may further include, in response to the determined identity information being corresponding to the identity information of the first access device, sending the data to the first access device.

Abstract: The present disclosure provides a method, an apparatus, a device, and a medium for processing a loop instruction set. The method includes: in response to obtaining a first start instruction of the loop instruction set, storing a first loop number related to the loop instruction set into a first register, and storing a value of a first program counter corresponding to a loop instruction following the first start instruction in the loop instruction set, into a second register. The method further includes: obtaining the loop instruction following the first start instruction in the loop instruction set for executing the loop instruction. The method further includes: in response to obtaining a first end instruction for indicating an end of the loop instruction set, determining a loop execution for the loop instruction set based on the first loop number and the value of the first program counter.

Abstract: Disclosed are a computing method applied to an artificial intelligence chip and the artificial intelligence chip.