Abstract: A PLL-VCO based integrated circuit aging monitor, including: a control circuit, a monitoring circuit, and an output circuit. The monitoring circuit includes a reference circuit, an aging generation circuit, and a comparison circuit. The reference circuit is a PLL circuit insensitive to a parameter error caused by the aging of circuit. The aging generation circuit is a VCO circuit sensitive to the parameter error. The control circuit is connected to the PLL circuit, the VCO circuit, the comparison circuit, and the output circuit. The output end of the PLL circuit is connected to a first input end of the comparison circuit, and the output end of the VCO circuit is connected to a second input end of the comparison circuit. The output end of the comparison circuit is connected to the input end of the output circuit. The input end of the PLL circuit inputs a reference clock signal.

Abstract: A physical unclonable function (PUF) circuit based on a zero temperature coefficient (ZTC) point of a metal oxide semiconductor field effect transistor (MOSFET), the PUF circuit including at least one PUF circuit unit. Each PUF circuit unit includes: a deviation signal generating circuit module, a signal selection circuit, and a comparison output circuit. The deviation signal generating circuit module includes two deviation signal generating circuits. A control voltage input terminal of the deviation signal generating circuit is supplied with a control voltage, and the control voltage enables a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS to work at a ZTC point.

Abstract: A PLL-VCO based integrated circuit aging monitor, including: a control circuit, a monitoring circuit, and an output circuit. The monitoring circuit includes a reference circuit, an aging generation circuit, and a comparison circuit. The reference circuit is a PLL circuit insensitive to a parameter error caused by the aging of circuit. The aging generation circuit is a VCO circuit sensitive to the parameter error. The control circuit is connected to the PLL circuit, the VCO circuit, the comparison circuit, and the output circuit. The output end of the PLL circuit is connected to a first input end of the comparison circuit, and the output end of the VCO circuit is connected to a second input end of the comparison circuit. The output end of the comparison circuit is connected to the input end of the output circuit. The input end of the PLL circuit inputs a reference clock signal.

Abstract: A physical unclonable function (PUF) circuit based on a zero temperature coefficient (ZTC) point of a metal oxide semiconductor field effect transistor (MOSFET), the PUF circuit including at least one PUF circuit unit. Each PUF circuit unit includes: a deviation signal generating circuit module, a signal selection circuit, and a comparison output circuit. The deviation signal generating circuit module includes two deviation signal generating circuits. A control voltage input terminal of the deviation signal generating circuit is supplied with a control voltage, and the control voltage enables a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS to work at a ZTC point.