Abstract: A method using at least a portion of a control data flow graph (CDFG) which includes multiple control structures in a computer readable storage medium representing at least a portion of a high level design language (HDL) description of an actual or planned logic circuit to evaluate a need for a sequential state element in the portion of the logic circuit comprising producing a graph structure in the storage medium by providing a path origination node in the storage medium; providing a path destination node in the storage medium; producing respective complete paths between the path origination node and the path destination node by separately concatenating each branch of a first control structure of the CDFG with each branch of a second control structure of the CDFG such that a different respective complete path is produced for each possible combination of a respective branch from the first control structure and a respective branch from the second control structure; associating respective complete paths with a

Abstract: A novel global placement process and associated computer software are provided for global placement of functional cells of an integrated circuit design. The global placement process is recursive and timing driven. Functional cells are placed according to how that placement is likely to influence signal timing. Also, a novel detailed placement process and associated computer software is provided for detailed placement of functional cells of an integrated circuit design. Target zones are defined which provide indications of the timing impact of functional cell movement. A detailed search for improved cell placements is conducted in which target zones are used to assess the signal timing impact of proposed cell movements. The novel global placement produces a global cell placement result, and the novel detailed placement process produces an improved detailed placement result.