Patents by Inventor Xueren Zhang

Xueren Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8486824
    Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: July 16, 2013
    Assignees: STMicroelectronics Asia Pacific PTE., Ltd., Nanyang Technological University
    Inventors: Tong Yan Tee, Xueren Zhang, Shanzhong Wang, Valeriy Nosik, Jijie Zhou, Sridhar Idapalapati, Subodh Mhaisalkar, Zhi Yuan Shane Loo
  • Publication number: 20130161806
    Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD.
    Inventors: Xueren ZHANG, Kim-Yong GOH, Wingshenq WONG
  • Publication number: 20130147052
    Abstract: An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventors: Xueren Zhang, Kim-Yong Goh
  • Publication number: 20130147024
    Abstract: An integrated circuit package structure includes a bottom portion having a cavity, an integrated circuit attached to a top surface of the stepped cavity, a leadframe attached to the bottom portion, wire bonding for electrically coupling the integrated circuit to the leadframe, and a top portion conformally covering the integrated circuit and the bottom portion.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: STMicroelectronics PTE Ltd.
    Inventors: Kim-Yong GOH, Xueren Zhang, Wingshenq Wong
  • Publication number: 20130093072
    Abstract: A leadframe includes a die pad and a protective wall surrounding the die pad. A semiconductor die is situated on the die pad. Indentations are formed on the four inner corners of the protective wall adjacent the corners of the semiconductor die.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventors: Xueren Zhang, Wingshenq Wong, Kim-Yong Goh, Yiyi Ma
  • Publication number: 20130012016
    Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 10, 2013
    Applicant: STMicroelectronics Asia Pacific PTE Ltd
    Inventors: Tong Yan Tee, Xueren Zhang, Shanzhong Wang, Valeriy Nosik, Jijie Zhou, Sridhar Idapalapati, Subodh Mhaisalkar, Zhi Yuan Shane Loo
  • Patent number: 8217518
    Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: July 10, 2012
    Assignees: STMicroelectronics Asia Pacific Pte., Ltd., Nanyang Technological University
    Inventors: Tong Yan Tee, Xueren Zhang, Shanzhong Wang, Valeriy Nosik, Jijie Zhou, Sridhar Idapalapati, Subodh Mhaisalkar, Zhi Yuan Shane Loo
  • Publication number: 20080178691
    Abstract: A force sensor to measure a force from a load. The force sensor includes a plunger, a flexible disc-shaped membrane, a support plate and a silicon die. The plunger is configured to receive the force from the load, and has a ring-shaped groove at the lower surface. The membrane has a ring-shaped upper bump at the upper surface, wherein the upper bump is configured to complementarily fit into the groove at the lower surface of plunger. Furthermore, the membrane has a ring-shaped lower bump at lower upper surface. The support plate has a ring-shaped groove that is configured so that the lower bump on the lower surface of the membrane can complementarily fit into. The silicon die is centrally mounted on the membrane, where the silicon die comprises piezo-resistors that vary their resistance when deformed by the force.
    Type: Application
    Filed: May 11, 2007
    Publication date: July 31, 2008
    Applicant: STMicroelectronics Asia Pacific PTE Ltd
    Inventors: Xueren Zhang, Andrea Lorenzo Vitali, Federico Giovanni Ziglioli, Bruno Biffi, Tong Yan Tee
  • Publication number: 20070216032
    Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 20, 2007
    Applicants: STMicroelectronics Asia Pacific PTE Ltd, Nanyang Technological University
    Inventors: Tong Tee, Xueren Zhang, Shanzhong Wang, Valeriy Nosik, Jijie Zhou, Sridhar Idapalapati, Subodh Mhaisalkar, Zhi Yuan Loo
  • Publication number: 20070210455
    Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 13, 2007
    Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD
    Inventors: Shanzhong Wang, Valeriy Nosik, Tong Tee, Xueren Zhang