Abstract: The present disclosure describes systems and methods for assigning nodes in a circuit design to layers. The method includes identifying a plurality of structures in a circuit design. Each of the plurality of structures includes four nodes of the circuit design and each of the four nodes are connected to every other node in the respective structure. The method also includes removing, from the plurality of structures, an even number of pairs of connected nodes of the circuit design to form a reduced node structure and assigning circuit layers for the nodes in the reduced node structure. The method further includes assigning, by a processing device, circuit layers for the pairs of connected nodes removed from the plurality of structures based on the assigned circuit layers for the nodes in the reduced node structure.