Patents by Inventor Xueru YU

Xueru YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12288725
    Abstract: The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD?) values, according to relative error between CD? and CD, dividing the rebuilt critical dimension (CD?) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 29, 2025
    Assignee: SHANGHAI IC R&D CENTER CO., LTD.
    Inventors: Xueru Yu, Hongxia Sun, Chen Li, Pengfei Wang, Jiebin Duan, Xiucui Wang, Hao Fu, Tao Zhou, Yan Yan, Bowen Xu, Lingyi Guo, Liren Li
  • Publication number: 20240379158
    Abstract: A memory and reading, writing and erasing methods thereof. The memory includes: H memory planes arranged in parallel along a first direction, where each memory plane extends in a second direction, and includes M columns of memory strings; each column of memory string extends in a third direction; the first direction, the second direction and the third direction are all different, and H and M are integers greater than zero; each column of memory string includes N rows of memristive memory cells. The memory is also provided with word lines, gating transistors, gating lines, bit lines and a common source line, where memristive memory cells in last rows of all memory strings are connected to the common source line, and the common source line is connected to a reference potential through a reference resistor. Use performance of the memory can be improved.
    Type: Application
    Filed: December 31, 2021
    Publication date: November 14, 2024
    Applicant: SHANGHAI IC R&D CENTER CO., LTD.
    Inventors: Lingyi GUO, Xueru YU
  • Publication number: 20220399237
    Abstract: The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD?) values, according to relative error between CD? and CD, dividing the rebuilt critical dimension (CD?) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results.
    Type: Application
    Filed: July 23, 2020
    Publication date: December 15, 2022
    Inventors: Xueru YU, Hongxia SUN, Chen LI, Pengfei WANG, Jiebin DUAN, Xiucui WANG, Hao FU, Tao ZHOU, Yan YAN, Bowen XU, Lingyi GUO, Liren LI