Patents by Inventor Xuesong Rao
Xuesong Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11610837Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.Type: GrantFiled: September 21, 2020Date of Patent: March 21, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Xuesong Rao, Benfu Lin, Bo Li, Chengang Feng, Yudi Setiawan, Yun Ling Tan
-
Patent number: 11545486Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film.Type: GrantFiled: October 2, 2020Date of Patent: January 3, 2023Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Chengang Feng, Yanxia Shao, Yudi Setiawan, Handoko Linewih, Xuesong Rao
-
Patent number: 11315876Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.Type: GrantFiled: February 17, 2020Date of Patent: April 26, 2022Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Xuesong Rao, Yun Ling Tan, Yudi Setiawan, Siow Lee Chwa
-
Publication number: 20220108980Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Inventors: Chengang FENG, Yanxia SHAO, Yudi SETIAWAN, Handoko LINEWIH, Xuesong RAO
-
Publication number: 20220093508Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.Type: ApplicationFiled: September 21, 2020Publication date: March 24, 2022Inventors: XUESONG RAO, BENFU LIN, BO LI, CHENGANG FENG, YUDI SETIAWAN, YUN LING TAN
-
Patent number: 11244915Abstract: A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.Type: GrantFiled: October 31, 2019Date of Patent: February 8, 2022Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ramasamy Chockalingam, Juan Boon Tan, Chee Kong Leong, Ranjan Rajoo, Xuesong Rao, Xiaodong Li
-
Publication number: 20210257300Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.Type: ApplicationFiled: February 17, 2020Publication date: August 19, 2021Inventors: XUESONG RAO, YUN LING TAN, YUDI SETIAWAN, SIOW LEE CHWA
-
Publication number: 20210134742Abstract: A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Inventors: RAMASAMY CHOCKALINGAM, JUAN BOON TAN, CHEE KONG LEONG, RANJAN RAJOO, XUESONG RAO, XIAODONG LI
-
Patent number: 9859236Abstract: Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers and methods for making the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a copper bonding structure having a contact surface. The copper bonding structure overlies the substrate. A passivation layer formed of silicon carbon nitride is disposed on the contact surface.Type: GrantFiled: August 3, 2015Date of Patent: January 2, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Meng Meng Chong, Xuesong Rao, Chim Seng Seet, Xiaohua Zhan
-
Patent number: 9627219Abstract: Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer.Type: GrantFiled: April 16, 2014Date of Patent: April 18, 2017Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lei Wang, Xuesong Rao, Wei Lu, Alex See
-
Publication number: 20170040272Abstract: Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers and methods for making the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a copper bonding structure having a contact surface. The copper bonding structure overlies the substrate. A passivation layer formed of silicon carbon nitride is disposed on the contact surface.Type: ApplicationFiled: August 3, 2015Publication date: February 9, 2017Inventors: Meng Meng Chong, Xuesong Rao, Chim Seng Seet, Xiaohua Zhan
-
Patent number: 9511470Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.Type: GrantFiled: January 25, 2016Date of Patent: December 6, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Benfu Lin, Lei Wang, Xuesong Rao, Wei Lu, Alex See
-
Publication number: 20160181197Abstract: Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.Type: ApplicationFiled: February 29, 2016Publication date: June 23, 2016Inventors: Xuesong RAO, Meng Meng Vanessa CHONG, Chim Seng SEET, Hendro MARIO, Aison JOHN GEORGE, Chor Shu CHENG
-
Patent number: 9349654Abstract: Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.Type: GrantFiled: March 28, 2014Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Liang Li, Xuesong Rao, Martina Damayanti, Wei Lu, Alex See, Yoke Leng Lim
-
Publication number: 20160136774Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.Type: ApplicationFiled: January 25, 2016Publication date: May 19, 2016Inventors: Benfu LIN, Lei WANG, Xuesong RAO, Wei LU, Alex SEE
-
Patent number: 9293388Abstract: Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.Type: GrantFiled: October 22, 2013Date of Patent: March 22, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Xuesong Rao, Meng Meng Vanessa Chong, Chim Seng Seet, Hendro Mario, Aison John George, Chor Shu Cheng
-
Patent number: 9242338Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.Type: GrantFiled: October 22, 2013Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Benfu Lin, Lei Wang, Xuesong Rao, Wei Lu, Alex See
-
Patent number: 9230886Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.Type: GrantFiled: December 18, 2014Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
-
Publication number: 20150303068Abstract: Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer.Type: ApplicationFiled: April 16, 2014Publication date: October 22, 2015Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lei WANG, Xuesong RAO, Wei LU, Alex SEE
-
Publication number: 20150279743Abstract: Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Liang LI, Xuesong RAO, Martina DAMAYANTI, Wei LU, Alex SEE, Yoke Leng LIM