Patents by Inventor Xuesong Zheng

Xuesong Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Refrigeration process
    Patent number: 9562717
    Abstract: The present invention relates to a single cycle mixed refrigerant process for industrial cooling applications, for example, the liquefaction of natural gas. The present invention also relates to a refrigeration assembly configured to implement the processes defined herein and a mixed refrigerant composition usable in such processes.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: February 7, 2017
    Assignee: The University of Manchester
    Inventors: Jin-Kuk Kim, Xuesong Zheng
  • CIRCUIT FOR LOW-POWER TERNARY DOMINO REVERSIBLE COUNTING UNIT
    Publication number: 20160094221
    Abstract: A circuit for a ternary Domino reversible counting unit. The circuit includes a ternary adiabatic Domino D flip-flop, a ternary adiabatic Domino positive and negative circulation port, and a ternary adiabatic Domino T-operation circuit. The ternary adiabatic Domino T-operation circuit includes a first signal input end, a second signal input end, and a third signal input end, a selection signal input end, a signal output end, a first clock signal input end, and a second clock signal input end. The positive and negative circulation port includes a signal input end, a borrow terminal, a carry terminal, a first output end, a second output end, a first clock signal input end, a second clock signal input end, and a third clock signal input end. The D flip-flop includes a signal input end, a reset terminal, a set terminal, a reverse-phase set terminal, a signal output end.
    Type: Application
    Filed: July 12, 2015
    Publication date: March 31, 2016
    Inventors: Pengjun WANG, Xuesong ZHENG, Yuejun ZHANG
  • Circuit for low-power ternary domino reversible counting unit
    Patent number: 9300290
    Abstract: A circuit for a ternary Domino reversible counting unit. The circuit includes a ternary adiabatic Domino D flip-flop, a ternary adiabatic Domino positive and negative circulation port, and a ternary adiabatic Domino T-operation circuit. The ternary adiabatic Domino T-operation circuit includes a first signal input end, a second signal input end, and a third signal input end, a selection signal input end, a signal output end, a first clock signal input end, and a second clock signal input end. The positive and negative circulation port includes a signal input end, a borrow terminal, a carry terminal, a first output end, a second output end, a first clock signal input end, a second clock signal input end, and a third clock signal input end. The D flip-flop includes a signal input end, a reset terminal, a set terminal, a reverse-phase set terminal, a signal output end.
    Type: Grant
    Filed: July 12, 2015
    Date of Patent: March 29, 2016
    Assignee: NINGBO UNIVERSITY
    Inventors: Pengjun Wang, Xuesong Zheng, Yuejun Zhang
  • Ternary T arithmetic circuit
    Patent number: 8937493
    Abstract: A ternary T arithmetic circuit, including: a logic 0 gate circuit, a logic 1 gate circuit, and a logic 2 gate circuit. The logic 0 gate circuit includes: a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, and a fifth NMOS. The logic 2 gate circuit includes: a fourth PMOS, a fifth PMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS. The logic 1 gate circuit includes: a sixth PMOS, a seventh PMOS, a ninth NMOS, a tenth NMOS, an eleventh NMOS, and a twelfth NMOS.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: January 20, 2015
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Xuesong Zheng, Qiankun Yang
  • TERNARY T ARITHMETIC CIRCUIT
    Publication number: 20140292373
    Abstract: A ternary T arithmetic circuit, including: a logic 0 gate circuit, a logic 1 gate circuit, and a logic 2 gate circuit. The logic 0 gate circuit includes: a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, and a fifth NMOS. The logic 2 gate circuit includes: a fourth PMOS, a fifth PMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS. The logic 1 gate circuit includes: a sixth PMOS, a seventh PMOS, a ninth NMOS, a tenth NMOS, an eleventh NMOS, and a twelfth NMOS.
    Type: Application
    Filed: March 20, 2014
    Publication date: October 2, 2014
    Applicant: NINGBO UNIVERSITY
    Inventors: Pengjun WANG, Xuesong ZHENG, Qiankun YANG
  • REFRIGERATION PROCESS
    Publication number: 20130008204
    Abstract: The present invention relates to a single cycle mixed refrigerant process for industrial cooling applications, for example, the liquefaction of natural gas. The present invention also relates to a refrigeration assembly configured to implement the processes defined herein and a mixed refrigerant composition usable in such processes.
    Type: Application
    Filed: March 25, 2011
    Publication date: January 10, 2013
    Applicant: UNIVERSITY OF MANCHESTER
    Inventors: Jin-Kuk Kim, Xuesong Zheng