Abstract: Disclosed are a pipelined successive approximation register analog-to-digital converter, an integrated circuit, and an electronic device. The pipelined successive approximation register analog-to-digital converter includes: a first-stage successive approximation register analog-to-digital converter (10), a residue amplifier (30), a second-stage successive approximation register analog-to-digital converter (20), and a digital coding unit (40).

Abstract: A clock data recovery circuit and a clock data recovery method are provided. The clock data recovery circuit includes a time delay loop (100), a frequency locking loop (200) and a deserializer (300). The time delay loop (100) is configured to delay input data according to a phase of a clock signal to realize phase alignment; the frequency locking loop (200) is connected to the time delay loop (100), and is configured to adjust a frequency of the clock signal according to the delayed input data to make the frequency of the clock signal be consistent with a frequency of the input data; and the deserializer (300) is respectively connected to the time delay loop (100) and the frequency locking loop (200), and is configured to deserialize the input data according to the clock signal.