Abstract: A double-balanced sinusoidal mixing phase interpolator circuit comprises: a double-balanced gain stage having a first input for receiving a first phasor clock, a second input for receiving a second phasor clock, and a phase interpolator (PI) output, wherein the double-balance gain stage includes (i) a first gain stage having a positive input side and a negative input side for the first phasor clock and (ii) a second gain stage having a positive input side and a negative input side for the second phasor clock; and a sinusoidal digital-to-analog (DAC) stage coupled to the double-balanced gain stage and configured to implement sinusoidal weighting of positive and negative sides of differential DAC current for the first phasor clock and positive and negative sides of differential DAC current for the second phasor clock, wherein the sinusoidal weighting provides uniformly spaced phase steps in the phase interpolator (PI) output.

Abstract: A square wave to pseudo-sinusoidal clock conversion circuit comprises first and second stages. The first stage includes a cross-coupled differential pairs input gain stage having positive and negative input sides. Responsive to a differential square wave clock input, the first stage provides a first pass balanced differential clock with pull-up and pull-down symmetry. The second stage comprises positive and negative output side push-pull with low pass filter circuits, wherein the positive and negative output side push-pull with low pass filter circuits are responsive to the first pass balanced differential clock from the first stage for producing an output pseudo-sinusoidal clock that comprises a nearly sinusoidal output with slew rate controlled and clock waveform pull-up and pull-down symmetry for each of a respective one of the positive and negative output sides.

Abstract: Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.

Abstract: Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.

Abstract: Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.

Abstract: Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.