Abstract: A display panel and a display apparatus are provided. A first base plate includes a first substrate, a transistor array layer, a pixel electrode layer, a common electrode layer, a first inorganic insulating layer, and a second inorganic insulating layer. The transistor array layer is provided on a side of the first substrate. The pixel electrode layer and the common electrode layer are arranged on a side of the transistor array layer away from the first substrate. The transistor array layer includes a transistor, the pixel electrode layer includes a pixel electrode, and the common electrode layer includes common electrodes. An insulating layer between the transistor array layer and one of the pixel electrode layer and the common electrode layer close to the transistor array layer is the first inorganic insulating layer. The second inorganic insulating layer is provided between the pixel electrode layer and the common electrode layer.

Abstract: Provided are an array substrate and display device. The array substrate includes a base substrate; a fingerprint recognition unit with a light sensing structure; a light blocking layer and an electrode connecting structure arranged at a side of the light sensing structure facing away from the base substrate. The light blocking layer is provided with a collimation hole. A vertical projection of the collimation hole on the base substrate is partially overlapped with a vertical projection of the light sensing structure on the base substrate. An insulation layer is arranged between the electrode connecting structure and the light sensing structure. The insulation layer is provided with an electrode via. The electrode connecting structure is connected to the light sensing structure through the electrode via. The vertical projection of the collimation hole on the base substrate is not overlapped with a vertical projection of the electrode via on the base substrate.

Abstract: The present application discloses a pixel structure and a display device. The pixel structure includes a scan line having a branch structure; and a semiconductor pattern intersecting with the scan line and the branch structure. The semiconductor pattern includes: a first channel region disposed below the scan line; a second channel region disposed below the branch structure; and doping regions respectively disposed at two sides of the first channel region and at two sides of the second channel region. Wherein, the width of the second channel region is less than the width of the first channel region. The pixel structure may improve the display performance of the display screen.

Abstract: A diode and its fabrication method are provided. The diode includes a substrate, a buffer layer on a side of the substrate, a first film layer, a second film layer and a third film layer. The first film layer is a polycrystalline silicon film layer; the second film layer is an amorphous silicon film layer; and the third film layer is one of the polycrystalline silicon film layer and the amorphous silicon film layer. The diode at least includes a first portion, a second portion, a third portion, a first electrode, and a second electrode. The first portion is located in the first film layer; the second portion is located in the second film layer; and the third portion is located in the third film layer. The first electrode is electrically connected to the first portion, and the second electrode is electrically connected to the third portion.

Abstract: The present disclosure provides a force sensor, a display panel, and a force detection method. The force sensor includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. A first resistor is connected between the first input terminal and the first output terminal. A first transistor and a second transistor are connected in parallel between the first output terminal and the second input terminal. A third transistor and a fourth transistor are connected in parallel between the second input terminal and the second output terminal. A further first resistor is connected between the second output terminal and the first input terminal. An equivalent resistance of the first transistor is equal to that of the fourth transistor, and an equivalent resistance of the second transistor is equal to that of the third transistor.

Abstract: The disclosure provides a display panel and a method for driving the display panel. The display panel includes a display area and a peripheral area surrounding the display area, and the display area includes one first display area and at least one second display area. The design according to embodiments of the disclosure release enough space occupied by the peripheral area at one side of the at least one second display area far away from the first display area, thus increasing display area in desired direction and a screen-to-total face ratio.

Abstract: A diode and its fabrication method are provided. The diode includes a substrate, a buffer layer on a side of the substrate, a first film layer, a second film layer and a third film layer. The first film layer is a polycrystalline silicon film layer; the second film layer is an amorphous silicon film layer; and the third film layer is one of the polycrystalline silicon film layer and the amorphous silicon film layer. The diode at least includes a first portion, a second portion, a third portion, a first electrode, and a second electrode. The first portion is located in the first film layer; the second portion is located in the second film layer; and the third portion is located in the third film layer. The first electrode is electrically connected to the first portion, and the second electrode is electrically connected to the third portion.

Abstract: Provided are an array substrate and display device. The array substrate includes a base substrate; a fingerprint recognition unit with a light sensing structure; a light blocking layer and an electrode connecting structure arranged at a side of the light sensing structure facing away from the base substrate. The light blocking layer is provided with a collimation hole. A vertical projection of the collimation hole on the base substrate is partially overlapped with a vertical projection of the light sensing structure on the base substrate. An insulation layer is arranged between the electrode connecting structure and the light sensing structure. The insulation layer is provided with an electrode via. The electrode connecting structure is connected to the light sensing structure through the electrode via. The vertical projection of the collimation hole on the base substrate is not overlapped with a vertical projection of the electrode via on the base substrate.

Abstract: An array substrate and a display panel are provided. The array substrate includes a non-display area and a display area. The non-display area includes a first non-display area and a second non-display area, and the display area includes a normal display area and a wiring area. The normal display area is surrounded by the first non-display area, the wiring area is surrounded by the normal display area, and the second non-display area is surrounded by the wiring area. The second non-display area comprises an opening area. In the solution, since the number of data lead lines in the same layer in the wiring area is reduced, a line distance between adjacent data lead lines is increased, thereby reducing coupling capacitance between adjacent data lead lines arranged in the same layer.

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a base substrate, and a bias voltage applying circuit and a plurality of semiconductor pressure sensors both disposed at a side of the base substrate. The bias voltage applying circuit is electrically connected to a first power supply signal inputting terminal and a second power supply signal inputting terminal of the semiconductor pressure sensor via a first power supply signal line and a second power supply signal line, respectively, to supply a bias voltage to the semiconductor pressure sensor. A concentration of the dopant ions is higher when the related semiconductor pressure sensor is closer to the bias voltage applying circuit, so that an electrical resistance value of said semiconductor pressure sensor is lower.

Abstract: Provided are an array substrate, a display panel and a display device. The array substrate includes a base substrate, and a plurality of first signal lines and a plurality of second signal lines insulated from each other on a side of the base substrate. When some of the plurality of first signal lines extend to the wiring region, the wiring of which is configured to be around the assembly setting area and forms a first signal line concentrated region, and a first signal line passing through the wiring region includes a first signal line body portion and a first signal line winding portion. When some of the plurality of second signal lines extend to the wiring region, the wiring of which is configured to be around the assembly setting area and forms a second signal line concentrated region.

Abstract: The present disclosure provides a force sensor, a display panel, and a force detection method. The force sensor includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. A first resistor is connected between the first input terminal and the first output terminal. A first transistor and a second transistor are connected in parallel between the first output terminal and the second input terminal. A third transistor and a fourth transistor are connected in parallel between the second input terminal and the second output terminal. A further first resistor is connected between the second output terminal and the first input terminal. An equivalent resistance of the first transistor is equal to that of the fourth transistor, and an equivalent resistance of the second transistor is equal to that of the third transistor.

Abstract: An array substrate and a display panel are provided. The array substrate includes a non-display area and a display area. The non-display area includes a first non-display area and a second non-display area, and the display area includes a normal display area and a wiring area. The normal display area is surrounded by the first non-display area, the wiring area is surrounded by the normal display area, and the second non-display area is surrounded by the wiring area. The second non-display area comprises an opening area. In the solution, since the number of data lead lines in the same layer in the wiring area is reduced, a line distance between adjacent data lead lines is increased, thereby reducing coupling capacitance between adjacent data lead lines arranged in the same layer.

Abstract: The disclosure provides a display panel and a method for driving the display panel. The display panel includes a display area and a peripheral area surrounding the display area, and the display area includes one first display area and at least one second display area. The design according to embodiments of the disclosure release enough space occupied by the peripheral area at one side of the at least one second display area far away from the first display area, thus increasing display area in desired direction and a screen-to-total face ratio.

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a base substrate, and a bias voltage applying circuit and a plurality of semiconductor pressure sensors both disposed at a side of the base substrate. The bias voltage applying circuit is electrically connected to a first power supply signal inputting terminal and a second power supply signal inputting terminal of the semiconductor pressure sensor via a first power supply signal line and a second power supply signal line, respectively, to supply a bias voltage to the semiconductor pressure sensor. A concentration of the dopant ions is higher when the related semiconductor pressure sensor is closer to the bias voltage applying circuit, so that an electrical resistance value of said semiconductor pressure sensor is lower.

Abstract: The invention discloses an array substrate, a display panel, and a display device, where at least one control capacitor is added to a pixel zone, and the control capacitor has a first electrode at a fixed potential, and a second electrode at the same potential as a node between two adjacent transistors, so that when an active gate scan signal is stopped from being loaded on a gate line, the potential of the second electrode of the control capacitor is controlled to be kept at the potential of data signal loaded on a data line, to thereby lower the difference in voltage between the source and the drain of a transistor associated with the second electrode of the control capacitor so as to keep the potential at a connection point of the transistor with a storage capacitor to be the potential of a data signal loaded on the data line.

Abstract: The invention discloses an array substrate, a display panel, and a display device, where at least one control capacitor is added to a pixel zone, and the control capacitor has a first electrode at a fixed potential, and a second electrode at the same potential as a node between two adjacent transistors, so that when an active gate scan signal is stopped from being loaded on a gate line, the potential of the second electrode of the control capacitor is controlled to be kept at the potential of data signal loaded on a data line, to thereby lower the difference in voltage between the source and the drain of a transistor associated with the second electrode of the control capacitor so as to keep the potential at a connection point of the transistor with a storage capacitor to be the potential of a data signal loaded on the data line.

Abstract: The present application discloses a pixel structure and a display device. The pixel structure includes: a scan line having a branch structure; and a semiconductor pattern intersecting with the scan line and the branch structure. The semiconductor pattern includes: a first channel region disposed below the scan line; a second channel region disposed below the branch structure; and doping regions respectively disposed at two sides of the first channel region and at two sides of the second channel region. Wherein, the width of the second channel region is less than the width of the first channel region. The pixel structure may improve the display performance of the display screen.