Abstract: A three-dimensional (3D) memory device and method for reading the same are provided. The device includes memory cell strings each including multiple memory cells. In each memory cell string, a topmost memory cell is connected to a top selection gate connected to a bit line, and a bottommost memory cell is connected to a bottom selection gate. The method includes sequentially programming multiple memory cells in a memory cell string according to a programming sequence; in reading a memory cell, applying a corresponding bit line voltage to the memory cell string according to the programming sequence of the memory cell.

Abstract: The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage.

Abstract: A three-dimensional (3D) memory device and method for reading the same are provided. The device includes memory cell strings each including multiple memory cells. In each memory cell string, a topmost memory cell is connected to a top selection gate connected to a bit line, and a bottommost memory cell is connected to a bottom selection gate. The method includes sequentially programming multiple memory cells in a memory cell string according to a programming sequence; in reading a memory cell, applying a corresponding bit line voltage to the memory cell string according to the programming sequence of the memory cell.

Abstract: Implementations of the present disclosure provide 3D memory devices and methods for operating the 3D memory devices. In an example, a 3D memory device includes a plurality of memory layers and a dummy memory layer between the plurality of memory layers and a NAND memory string extending through the memory layers and the dummy memory layer. The NAND memory string includes a source, a drain, and a plurality of memory cells at intersections with the plurality of memory layers and between the source and the drain. The 3D memory device also includes a peripheral circuit configured to erase the plurality of memory cells. To erase the plurality of memory cells, the peripheral circuit includes a word line driving circuit configured to apply a positive bias voltage on the dummy memory layer.

Abstract: Implementations of the present disclosure provide 3D memory devices and methods for operating the 3D memory devices. In an example, a 3D memory device includes a plurality of memory layers and a dummy memory layer between the plurality of memory layers and a NAND memory string extending through the memory layers and the dummy memory layer. The NAND memory string includes a source, a drain, and a plurality of memory cells at intersections with the plurality of memory layers and between the source and the drain. The 3D memory device also includes a peripheral circuit configured to erase the plurality of memory cells. To erase the plurality of memory cells, the peripheral circuit includes a word line driving circuit configured to apply a positive bias voltage on the dummy memory layer.

Abstract: The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage.