Patents by Inventor Xuliang Zhou

Xuliang Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing Si-based high-mobility group III-V/Ge channel CMOS
    Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • METHOD OF MANUFACTURING SI-BASED HIGH-MOBILITY GROUP III-V/GE CHANNEL CMOS
    Publication number: 20150024601
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Application
    Filed: March 21, 2014
    Publication date: January 22, 2015
    Applicant: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang