Abstract: A strongly confined ridge waveguide that provides substantially reduced polarization sensitivity, without significant compromise for other waveguide characteristics such as, for example, single-mode condition, and low propagation and bending losses for the fundamental mode. The present invention considers waveguide material composition and thickness for guiding and cladding layers, bend radius, ridge width and etch depth at which the modal indices of the fundamental TE and TM modes are equal. With those parameters, the losses (e.g., the imaginary parts of the modal indices) of the fundamental and first-order modes may be calculated. By considering the previously mentioned criteria, a low-loss, single-mode ridge waveguide may be constructed in accordance with the present invention having losses of the fundamental modes in the range of less than approximately 1.

Abstract: A method for forming a CMOS transistor gate with a self-aligned. channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshhold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.

Abstract: A method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshhold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.

Abstract: A method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.

Abstract: A guided wave optical switch having a passive optical component optically coupled to a low gain optical amplifier—both being formed monolithically in a semiconductor substrate. The passive optical component may comprise a single-mode −3 dB optical power splitter that receives at an input an optical signal and splits that optical signal approximately equally between two outputs. The passive optical component may also comprise an optical isolator, an optical circulator, and other known passive optical devices. The low gain optical amplifier includes a waveguide having an active region that may provide optical signal gain when excited by an electrical current provided by a metal or metallic electrode connected to the active region. The active region may be a bulk active region, a multiple quantum well active region, or the waveguide may comprise a buried heterojunction waveguide having either a bulk or multiple quantum well active region.

Abstract: A method for forming, within a low dielectric constant dielectric layer formed upon a substrate employed within a microelectronics fabrication, a conductor pattern employing a hard mask cap layer. There is first provided a substrate having conductor regions formed therein upon which is formed a low dielectric constant dielectric layer. There is then formed over the substrate a silicon containing hard mask cap layer. There is then formed over the hard mask cap layer a patterned photoresist etch mask layer. There is then subtractively etched employing the patterned photoresist etch mask layer and a first subtractive etching environment the pattern into the hard mask layer. There is then subtractively etched employing the patterned hard mask layer and a second etching environment the pattern into the low dielectric constant dielectric layer, simultaneously stripping the photoresist etch mask layer.

Abstract: A process for the preparation of a compound of formula I 1

Abstract: A surface-emitting optical amplifier having a generally circular waveguide and active region. The waveguide and active region match the shape of an optical fiber or other device for generating, transmitting, guiding, propagating, etc., an optical signal. For example, the shape of the waveguide and active region may be circular, elliptical, square, rectangular, or virtually any other required shape. By matching the shape of the waveguide and active region to the shape of the device to which the waveguide connects, coupling loss is reduced and polarization dependent loss is eliminated due to the symmetry of the active region. The reduction of the coupling loss also leads to an increase of the signal to noise ratio since the signal loss from the input coupling is directly reduced.

Abstract: A strongly confined ridge waveguide that provides substantially reduced polarization sensitivity, without significant compromise for other waveguide characteristics such as, for example, single-mode condition, and low propagation and bending losses for the fundamental mode. The present invention considers waveguide material composition and thickness for guiding and cladding layers, bend radius, ridge width and etch depth at which the modal indices of the fundamental TE and TM modes are equal. With those parameters, the losses (e.g., the imaginary parts of the modal indices) of the fundamental and first-order modes may be calculated. By considering the previously mentioned criteria, a low-loss, single-mode ridge waveguide may be constructed in accordance with the present invention having losses of the fundamental modes in the range of less than approximately 1.

Abstract: A method of forming a shallow trench isolation trenches in a silicon substrate of an integrated circuit device is achieved. A silicon substrate is provided. A buffer layer is deposited overlying the silicon substrate. An etching endpoint layer is deposited overlying the buffer layer. A silicon layer is deposited layer overlying the etching endpoint layer. A photoresist layer is coated overlying the silicon layer. The photoresist layer is developed wherein the photoresist layer is removed where the trenches are planned. The silicon layer, the etching endpoint layer, and the buffer layer are etched through to expose the top surface of the silicon substrate. The silicon layer and the silicon substrate layer are etched until the top surface of the etching endpoint layer is exposed, and the trenches are thereby formed. The integrated circuit device is completed.

Abstract: A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a pair of microelectronic structures. There is then formed sequentially upon the substrate including the pair of microelectronic structures a first conformal dielectric layer followed by a second conformal dielectric layer followed by a third dielectric layer, where the second conformal dielectric layer serves as an etch stop layer with respect to the third dielectric layer in a first plasma etch method employed in forming in part a via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer at a location between the pair of microelectronic structures.

Abstract: Silicon enriched silicon oxynitride is used in applications both as an independent etch stop and as a cap layer and sidewall component over polysilicon gate electrodes in order to prevent insulator thinning and shorts caused by a mis-aligned contact mask. In one embodiment a silicon enriched silicon oxynitride layer is placed over a polysilicon gate with conventional sidewalls and insulative cap. In another embodiment the insulative cap and the sidewalls are formed of a silicon enriched silicon oxinitride. Etching of contact openings in the subsequently deposited insulative layer is suppressed by the silicon enriched silicon oxynitride if it is engaged because of a mis-aligned contact mask. In another embodiment a polysilicon stack edge of a memory device is protected by a conformal silicon oxynitride layer during etching of a self-aligned-source (SAS) region. These embodiments are accomplished with minimal and virtually negligible increase in process complexity or cost.

Abstract: The invention pertains to the field of DNA detection for basic research, medical diagnostic testing, and forensic testing. Methods are provided for end labeling of DNA strands without a denaturation step so that cellular morphology can be better preserved. The DNA strands are first incubated with a halogenated deoxynucleotide triphosphate, such as brominated deoxyuridine triphosphate (BrdUTP), and an enzyme which can catalyze the addition of the halogenated deoxynucleotide to the 3' OH ends of the DNA strand, such as terminal deoxynucleotidyl transferase (TdT). The resulting modified DNA strands are then incubated with a labeled antibody, such as a fluoresceinated monoclonal antibody, that binds specifically to the halogenated deoxynucleotide. The label is then detected, e.g., by flow cytometry. The methods have utility in detecting apotosis, DNA synthesis and/or repair, and as general methods for end labeling DNA.

Abstract: A process for fabricating a large surface area, storage node structure, for a DRAM device, has been developed. The storage node structure is comprised of a lower level polysilicon structure, exhibiting a "twin hammer tree" shape, and connected to an upper polysilicon level, exhibiting a "branch" type shape. The fabrication process used to create this storage node structure, features various deposition procedures, used for insulator and polysilicon layers, and various anisotropic and isotropic, dry etch procedures, as well as wet etch procedures, used for creation of the "twin hammer tree" shaped structure.

Abstract: A method for detecting halogenated precursors incorporated into DNA is presented. The method is based on the selective photolysis of DNA by ultraviolet (UV) light at the sites of an incorporated halogenated precursor, such as the thymidine base analogs 5-bromo-2-deoxyuridine (BrdUrd), 5-iodo-2-deoxyuridine (IdUrd), 5-fluoro-2-deoxyuridine (FdUrd), or 5-chloro-2-deoxyuridine (CldUrd). The 3'-hydroxyl termini of the DNA single strand breaks generated during photolysis may be marked directly or indirectly with a fluorescent label. The DNA termini are directly labeled with fluorochrome-conjugated deoxyuridine triphosphate (dUTP) catalyzed by exogenous terminal deoxynucleotidyl transferase or DNA polymerase (nick translation system). The DNA termini are indirectly labeled with either biotin- or digoxygenin-conjugated dUTP; the incorporated biotin or digoxygenin is then detected following binding of fluorochrome-conjugated avidin or anti-digoxygenin antibody, respectively.