Patents by Inventor Xun MOU

Xun MOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797087
    Abstract: An array substrate, a method for manufacturing an array substrate and a display device are provided. The array substrate includes: a base substrate, and an insulating layer, a gate line, a source electrode, a drain electrode, and a data line on the base substrate. The insulating layer includes a light transmission portion and a light shielding portion, and orthographic projections of the gate line, the source electrode, the drain electrode, and the data line on the base substrate are all within an orthographic projection of the light shielding portion on the base substrate.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: October 6, 2020
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhengdong Zhang, Gang Zhou, Hua Tian, Xiaofei Yang, Ke Dai, Lei Su, Xun Mou
  • Patent number: 10644037
    Abstract: The present disclosure relates to a via-hole connection structure and a method of manufacturing the same and an array substrate and a method of manufacturing the same. In an embodiment, a method of manufacturing a via-hole connection structure, includes the following steps of: forming a first conductive layer on a substrate, and patterning the first conductive layer to form a first conductive pattern on which a first photoresist pattern is provided; forming a first insulation layer covering the first conductive layer and the first photoresist pattern; patterning the first insulation layer to form a first via-hole from which at least a portion of the first photoresist pattern is exposed; removing the at least a portion of the first photoresist pattern exposed from the first via-hole; and forming a second conductive pattern, wherein the second conductive pattern is electrically connected to the first conductive pattern through the first via-hole.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 5, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELETRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Su, Xiaofei Yang, Xu Liu, Xun Mou, Yawen Zhu
  • Publication number: 20190214411
    Abstract: An array substrate, a method for manufacturing an array substrate and a display device are provided. The array substrate includes: a base substrate, and an insulating layer, a gate line, a source electrode, a drain electrode, and a data line on the base substrate. The insulating layer includes a light transmission portion and a light shielding portion, and orthographic projections of the gate line, the source electrode, the drain electrode, and the data line on the base substrate are all within an orthographic projection of the light shielding portion on the base substrate.
    Type: Application
    Filed: June 14, 2018
    Publication date: July 11, 2019
    Inventors: Zhengdong ZHANG, Gang ZHOU, Hua TIAN, Xiaofei YANG, Ke DAI, Lei SU, Xun MOU
  • Publication number: 20190131316
    Abstract: The present disclosure relates to a via-hole connection structure and a method of manufacturing the same and an array substrate and a method of manufacturing the same. In an embodiment, a method of manufacturing a via-hole connection structure, includes the following steps of: forming a first conductive layer on a substrate, and patterning the first conductive layer to form a first conductive pattern on which a first photoresist pattern is provided; forming a first insulation layer covering the first conductive layer and the first photoresist pattern; patterning the first insulation layer to form a first via-hole from which at least a portion of the first photoresist pattern is exposed; removing the at least a portion of the first photoresist pattern exposed from the first via-hole; and forming a second conductive pattern, wherein the second conductive pattern is electrically connected to the first conductive pattern through the first via-hole.
    Type: Application
    Filed: March 26, 2018
    Publication date: May 2, 2019
    Inventors: Lei Su, Xiaofei Yang, Xu Liu, Xun Mou, Yawen Zhu
  • Patent number: 10025143
    Abstract: An array substrate and a fabrication method thereof and a display device are provided. The array substrate comprises: a base substrate; a plurality of gate lines and a plurality of data lines formed on the base substrate, the plurality of gate lines and the plurality of data lines intersecting with each other to define a plurality of sub-pixels, each of the sub-pixels including a thin film transistor and a pixel electrode, and the plurality of sub-pixels including a first sub-pixel; a passivation layer formed on the base substrate and covering the gate lines, the data lines and the thin film transistor, a via hole being provided in the passivation layer and the pixel electrode being formed on the passivation layer and connected with a drain electrode or a source electrode of the thin film transistor through the via hole in each of the sub-pixels; and a first spacer, provided in the via hole of the first sub-pixel.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: July 17, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaofei Yang, Yuqing Yang, Yanxia Xin, Zailong Mo, Xue Jiang, Xun Mou
  • Publication number: 20180107299
    Abstract: The present disclosure discloses a touch substrate including a substrate, and an arrangement of a plurality of touch electrode lines provided on the substrate, each of the touch electrode lines including a plurality of line segments substantially in the form of a zigzag, wherein each of the line segments includes a plurality of small segments of a polyline, or is an approximate arc.
    Type: Application
    Filed: February 16, 2017
    Publication date: April 19, 2018
    Inventors: Haoyuan FAN, Xun MOU, Huiguang YANG, Qian WU
  • Publication number: 20170146844
    Abstract: An array substrate and a fabrication method thereof and a display device are provided. The array substrate comprises: a base substrate (1); a plurality of gate lines (5) and a plurality of data lines (7) formed on the base substrate (1), the plurality of gate lines (5) and the plurality of data lines (7) intersecting with each other to define a plurality of sub-pixels, each of the sub-pixels including a thin film transistor and a pixel electrode (10), and the plurality of sub-pixels including a first sub-pixel; a passivation layer (8) formed on the base substrate (1) and covering the gate lines (5), the data lines (7) and the thin film transistor, a via hole (9) being provided in the passivation layer (8) and the pixel electrode (10) being formed on the passivation layer (8) and connected with a drain electrode or a source electrode of the thin film transistor through the via hole (9) in each of the sub-pixels; and a first spacer (15), provided in the via hole of the first sub-pixel.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 25, 2017
    Inventors: Xiaofei YANG, Yuqing YANG, Yanxia XIN, Zailong MO, Xue JIANG, Xun MOU
  • Patent number: 5834644
    Abstract: An atomic force microscope which can provide an automatic operation of focusing a laser beam onto a cantilever of the atomic force microscope, and which can ensure that a laser beam reflected off this cantilever is properly directed to a detector. A tip supported by the cantilever can also be automatically and properly lowered to a specimen. A piezotube scanner within such an atomic force microscope is also provided to prevent any damage from occurring if any leakage of an aqueous solution containing the specimen occurs.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: November 10, 1998
    Assignee: The University of Virginia Patent Foundation
    Inventors: Zhifeng Shao, Jian Xun Mou, Gang Huang