Abstract: Provided is an array substrate, having a plurality of sub-pixel regions. The array substrate includes: a substrate; a pixel electrode layer and a common electrode layer that are disposed on the substrate; and a plurality of common signal lines disposed on the substrate. The plurality of common signal lines are insulated from the pixel electrode layer and electrically connected to the common electrode layer. An overlapped region is present between an orthographic projection of the common signal lines on the substrate and an orthographic projection of the pixel electrode layer on the substrate. The common signal lines have a plurality of electrode structures, wherein different electrode structures of the plurality of electrodes structures are disposed in different sub-pixel regions, and the plurality of electrode structures include a lap electrode lapped to the common electrode layer and an auxiliary electrode not lapped to the common electrode layer.

Abstract: Provided is an array substrate. The array substrate includes a substrate, comprising a display region and a peripheral region surrounding the display region, the peripheral region at least including a gate-driver-on-array (GOA) region extending in a first direction; a plurality of thin film transistors, the plurality of thin film transistors being disposed at least in the GOA region; and a plurality of first patterns, wherein the plurality of first patterns are disposed at least on one side of the GOA region, the plurality of first patterns are spaced apart from the GOA region in the first direction, and a plurality of first patterns disposed on a same side of the GOA region are arranged in an array.

Abstract: A display substrate is provided to include: a first base substrate including a sealing region and a display port region, wherein at least one first connection region and at least one second connection region are in the display port region, a first overlapping region is formed between the second and first connection regions; first and second connection terminals in the first and second connection regions, respectively; and a planarization layer including at least one first trench and at least one second trench corresponding to the first and second connection regions therein, respectively; orthographic projections of bottoms of first and second trenches on the first base substrate cover corresponding first and second connection regions, respectively; the planarization layer includes: a first pattern corresponding to the first overlapping region; orthographic projections of the first pattern and its corresponding first overlapping region on the first base substrate overlap with each other.

Abstract: A display substrate, including a plurality of gate lines and a plurality of data lines defining a plurality of pixel regions, where the plurality of pixel regions include a plurality of normal pixel regions and a plurality of redundant pixel regions at a periphery of the normal pixel regions; where each normal pixel region is provided with a first pixel electrode and a first transistor, each redundant pixel region is provided with a second pixel electrode and a second transistor, a gate of the first transistor is connected to a corresponding gate line, a source of the first transistor is connected to a corresponding data line, and a drain of the first transistor is connected to the first pixel electrode; and the second pixel electrode and the second transistor are insulated and spaced apart from each other.

Abstract: A display panel, a circuit board and a display device are provided. The display panel includes a first pad region including a first pad connected to a first integrated circuit, a second pad region including a second pad electrically connected to a second integrated circuit, a third pad region including third pads electrically connected to a circuit board and a common signal line electrically connected to the common electrode of the sub-pixel. The display panel further includes a first signal line and a second signal line, the first pad is electrically connected to the third pad through the first signal line, the second pad is electrically connected to the third pad through the second signal line; the first signal line and the second signal line are electrically connected to each other through the third pads and the circuit board.

Abstract: An array substrate (000) and a display apparatus, relating to the technical field of display. The array substrate (000) comprises: a substrate (100); a pixel electrode layer (200) and a common electrode layer (300) located on the substrate (100); and a plurality of common signal lines (400) located on the substrate (100), wherein the common signal lines (400) are insulated from the pixel electrode layer (200) and electrically connected to the common electrode layer (300), and an orthographic projection of the common signal lines (400) on the substrate (100) and an orthographic projection of the pixel electrode layer (200) on the substrate (100) have an overlapping area.

Abstract: Provided are a display substrate, display panel and display device. The display substrate comprises: a base substrate, comprising a display area and a surrounding area comprising a gluing area; multiple signal lines; multiple fanout lines, connected to multiple signal lines in a one-to-one correspondence manner. The fanout lines comprise: a first fanout line, and a second fanout line located at the side of first fanout line away from the base substrate; at least in the gluing area, the orthographic projection of the second fanout line on the base substrate substantially overlaps that of the first fanout line on the base substrate; in part of the area outside the gluing area, the size of an overlapping area between orthographic projections of the second fanout line and first fanout line on the base substrate in the direction perpendicular to the extension direction of the fanout lines is smaller than a first preset threshold.

Abstract: Provided is a thin film transistor unit. The thin film transistor unit includes a first gate, a first gate insulating layer, a first semiconductor layer and a first source/drain electrode layer that are sequentially arranged on a substrate, wherein the first source/drain electrode layer includes a first source and a first drain that are spaced apart from each other along a first direction; and a floating electrode disposed on a side of the first semiconductor layer away from the first gate insulating layer, wherein in the first direction, an orthographic projection of the floating electrode on the substrate falls between an orthographic projection of the first source on the substrate and an orthographic projection of the first drain on the substrate.

Abstract: A display panel, a circuit board and a display device are provided. The display panel includes a first pad region including a first pad connected to a first integrated circuit, a second pad region including a second pad electrically connected to a second integrated circuit, a third pad region including third pads electrically connected to a circuit board and a common signal line electrically connected to the common electrode of the sub-pixel. The display panel further includes a first signal line and a second signal line, the first pad is electrically connected to the third pad through the first signal line, the second pad is electrically connected to the third pad through the second signal line; the first signal line and the second signal line are electrically connected to each other through the third pads and the circuit board.

Abstract: The disclosure provides a display panel and a display device, and belongs to the technical field of display. The disclosure provides a display panel including a central display region and a bent display region at an edge of the central display region. The central display region is provided with a plurality of first pixels, and the bent display region is provided with a plurality of second pixels. A number of second pixels in a unit area is greater than a number of first pixels in the unit area. In the display panel, the PPI of the bent display region is higher than that of the central display region, so the number of the second pixels for gray-scale transition in the bent display region is increased, the gray-scale transition in the bent display region is uniform, and the aliasing phenomenon at the edge of the bent display region is improved.

Abstract: Provided are a display substrate, display panel and display device. The display substrate comprises: a base substrate, comprising a display area and a surrounding area comprising a gluing area; multiple signal lines; multiple fanout lines, connected to multiple signal lines in a one-to-one correspondence manner. The fanout lines comprise: a first fanout line, and a second fanout line located at the side of first fanout line away from the base substrate; at least in the gluing area, the orthographic projection of the second fanout line on the base substrate substantially overlaps that of the first fanout line on the base substrate; in part of the area outside the gluing area, the size of an overlapping area between orthographic projections of the second fanout line and first fanout line on the base substrate in the direction perpendicular to the extension direction of the fanout lines is smaller than a first preset threshold.

Abstract: A shift register includes a pull-up node, an output control sub-circuit, a first energy storage sub-circuit and an output sub-circuit. The output control sub-circuit is coupled to the pull-up node, a first clock signal terminal and the first energy storage sub-circuit, and is configured to transmit a first clock signal to the first energy storage sub-circuit under control of a voltage of the pull-up node. The first energy storage sub-circuit is coupled to the pull-up node and the output control sub-circuit, and is configured to store the voltage of the pull-up node, and boost the voltage of the pull-up node under action of the first clock signal. The output sub-circuit is coupled to the pull-up node and a signal output terminal, and is configured to transmit the boosted voltage of the pull-up node to the signal output terminal under the control of the voltage of the pull-up node.

Abstract: A method for determining a touch layer pattern, a touch display device, a computer device and a storage medium are provided. The method includes: providing a pixel pattern which contains a light shielding region and a sub-pixel region defined by the light shielding region; superimposing at least two different touch patterns with the pixel pattern respectively to obtain at least two superimposed patterns; and determining, as a touch layer pattern, a touch pattern from the at least two touch patterns, according to equivalent grayscales of the at least two superimposed patterns.

Abstract: A pixel circuit includes a data writing and compensation sub-circuit, a driving sub-circuit, and a light-emitting control sub-circuit. The data writing and compensation sub-circuit is configured to transmit a data signal from a data voltage terminal to the driving sub-circuit under control of a first control signal terminal, and to compensate a threshold voltage of the driving sub-circuit under the control of the first control signal terminal. The light-emitting control sub-circuit is configured to transmit a first voltage signal from a first voltage terminal to the driving sub-circuit and the data writing and compensation sub-circuit under control of a second control signal terminal, and to transmit a second voltage signal from the second voltage terminal to the driving sub-circuit under the control of the second control signal terminal. The driving sub-circuit is configured to transmit a signal output from the light-emitting control sub-circuit to a light-emitting sub-circuit.

Abstract: A touch display panel, a method for driving the same, and a display device.

Abstract: A test device and a test method are provided. The test device can comprise a movable probe platform, a plurality of signal access points, and a plurality of test probes fixed on the movable probe platform. Each of the plurality of signal access points is correspondingly coupled to one test probe for accessing a corresponding test signal. The plurality of the test probes are configured to contact with test pads on a panel to be tested, and to transmit test signals accessed from the plurality of the signal access points to the test pads, so as to perform an electrical test to the panel to be tested.

Abstract: Embodiments of the present disclosure provide a shift register and a driving method thereof and a gate driving circuit. The shift register comprises an inputting circuit, a first outputting circuit, and a second outputting circuit. The first outputting circuit may comprise a first pulling-up sub-circuit, a first outputting sub-circuit, a first pulling-down sub-circuit, and a switching sub-circuit. A controlling terminal of switching sub-circuit is coupled to a controlling terminal of the first pulling-up sub-circuit. An inputting terminal of the switching sub-circuit is coupled to the outputting terminal of a first outputting sub-circuit. The second outputting circuit may comprise a second pulling-up sub-circuit, a second outputting sub-circuit, and a second pulling-down sub-circuit. An inputting terminal of the second pulling-up sub-circuit is coupled to an outputting terminal of the switching sub-circuit.

Abstract: A touch display panel, a method for driving the same, and a display device.

Abstract: A shift register unit and a driving method thereof, a gate driving circuit and a display panel are disclosed. In the shift register unit of the embodiments of the present disclosure, at least two transistors are configured to be coupled to a DC signal supplying terminal. The at least two transistors are controlled to be alternatively turned on by an inputting signal from the DC signal supplying terminal.

Abstract: A touch display screen, a method for manufacturing the same, and a touch display device are provided. The touch display screen includes a display panel and a touch sensing pattern disposed on the display panel, an orthographic projection of the touch sensing pattern on the display panel covers a display region of the display panel and extends in a non-display region.